SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.9.2.1 FSI_RX_CFG_RX_MASTER_CTRL_ALTC Register

9.2.1.1 FSI_RX_CFG_RX_MASTER_CTRL_ALTC Register (Offset = 0h) [reset = 0h]

Receive master control register.

Table 3-994 Instance Table

Instance Name	Physical Address
FSI_RX0	5029 0000h
FSI_RX1	5029 1000h
FSI_RX2	502B 0000h
FSI_RX3	502B 1000h

Figure 3-466 FSI_RX_CFG_RX_MASTER_CTRL_ALTC Name Register

15	14	13	12	11	10	9	8
KEY
W
0h
7	6	5	4	3	2	1	0
RESERVED_1			DATA_FILTER_EN	INPUT_ISOLATE	SPI_PAIRING	INT_LOOPBACK	CORE_RST
R			R/W	R/W	R/W	R/W	R/W
0h			0h	0h	0h	0h	0h

Table 3-995 FSI_RX_CFG_RX_MASTER_CTRL_ALTC Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	KEY	W	0h	Write Key. In order to write to this register, 0xA5 must be written to this field at the same time. Otherwise, writes are ignored. The key is cleared immediately after Writing, so it must be written again for every change to this register.
7:5	RESERVED_1	R	0h	Reserved
4	DATA_FILTER_EN	R/W	0h	Data Filter Enable Bit. 0h[R/W] = Data filtering is disabled. 1h[R/W] = Data filtering is enabled.
3	INPUT_ISOLATE	R/W	0h	When set to 1, the FSI RX inputs [RXCLK, RXD0 and RXD1] will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of device pins and hence any potential glitch that could occur during the process of switching will not effect the RX module itself.
2	SPI_PAIRING	R/W	0h	Clock Pairing for SPI-like Behavior Enable bit This bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module, acting as a SPI master, to clock data into the receiver and out of the transmitter like a standard SPI module. This configuration is valid when the Module is in SPI mode only [RX_OPER_CTRL.SPI_MODE = 1] 0h[R/W] = SPI clock pairing is not enabled. 1h[R/W] = SPI clock pairing is enabled. The RXCLK will be internally connected to the TXCLK of the corresponding FSI module. Note: The KEY field must contatin 0xA5 for any write to this bit to take effect.
1	INT_LOOPBACK	R/W	0h	Internal Loopback Enable bit This bit enables the internal loopback functionality of the FSI receiver. By enabling this bit, a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the pins. 0h[R/W] = Internal loopback is disabled. The FSI RX module will receive signals coming from the pins. 1h[R/W] = Internal loopback is enabled. The FSI RX module will receive signals from the directly from FSI TX module rather than the pins. Note: The KEY field must contatin 0xA5 for any write to this bit to take effect.
0	CORE_RST	R/W	0h	Receiver Controller Core Reset bit This bit controls the receiver master core reset. In order to receive any frame, this bit must be cleared. Note: For reset to take affect, the FSI RX module must be held in reset for at least 4 SYSCLK cycles. 0h[R/W] = Receiver core is not in reset and can receive frames. 1h[R/W] = Receiver core is held in reset. Note: The KEY field must contatin 0xA5 for any write to this bit to take effect.