SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Receive DMA event control register.
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Instance Name | Physical Address |
---|---|
FSI_RX0 | 5029 0010h |
FSI_RX1 | 5029 1010h |
FSI_RX2 | 502B 0010h |
FSI_RX3 | 502B 1010h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_1 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | DMA_EVT_EN | ||||||
R | R/W | ||||||
0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:1 | RESERVED_1 | R | 0h | Reserved |
0 | DMA_EVT_EN | R/W | 0h | DMA Event Enable bit This bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h[R/W] = A DMA event will not be generated. 1h[R/W] = A DMA event will be generated upon the reception of a frame. Note: The DMA event will only be generated for data frames. |