SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Receive event and error status flag register.
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Instance Name | Physical Address |
---|---|
FSI_RX0 | 5029 0014h |
FSI_RX1 | 5029 1014h |
FSI_RX2 | 502B 0014h |
FSI_RX3 | 502B 1014h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_1 | ERROR_TAG_MATCH | DATA_TAG_MATCH | PING_TAG_MATCH | DATA_FRAME | FRAME_OVERRUN | PING_FRAME | ERR_FRAME |
R | R | R | R | R | R | R | R |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUF_UNDERRUN | FRAME_DONE | BUF_OVERRUN | EOF_ERR | TYPE_ERR | CRC_ERR | FRAME_WD_TO | PING_WD_TO |
R | R | R | R | R | R | R | R |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED_1 | R | 0h | Reserved |
14 | ERROR_TAG_MATCH | R | 0h | Error Tag Match Flag This bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No tag-matched error frame received. 1h[R] = A tag-matched error frame has been received. To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
13 | DATA_TAG_MATCH | R | 0h | Data Tag Match Flag This bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No tag-matched data frame received. 1h[R] = A tag-matched data frame has been received. To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
12 | PING_TAG_MATCH | R | 0h | Ping Tag Match Flag This bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No tag-matched ping frame received. 1h[R] = A tag-matched ping frame has been received. To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
11 | DATA_FRAME | R | 0h | Data Frame Received Flag This bit indicates that an data frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No data frame has been received. 1h[R] = A data frame has been received. To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
10 | FRAME_OVERRUN | R | 0h | Frame Overrun Flag This bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Frame overrun has not ocurred. 1h[R] = Frame overrun has ocurred. To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
9 | PING_FRAME | R | 0h | Ping Frame Received Flag This bit indicates that an ping frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No ping frame has been received. 1h[R] = A ping frame has been received. To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
8 | ERR_FRAME | R | 0h | Error Frame Received Flag This bit indicates that an error frame has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No error frame has been received. 1h[R] = An error frame has been received. To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
7 | BUF_UNDERRUN | R | 0h | Receive Buffer Underrun Flag This bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Receive Buffer Underrun has not ocurred. 1h[R] = Receive Buffer Underrun has ocurred. To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
6 | FRAME_DONE | R | 0h | Frame Done Flag This bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = No frame has been successfully received. 1h[R] = A frame has been successfully received. To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
5 | BUF_OVERRUN | R | 0h | Receive Buffer Overrun Flag This bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Receive buffer overrun has not ocurred. 1h[R] = Receive buffer overrun has ocurred. To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
4 | EOF_ERR | R | 0h | End-of-Frame Error Flag This bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Invalid end-of-frame has not been received. 1h[R] = Invalid end-of-frame has been received To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
3 | TYPE_ERR | R | 0h | Frame Type Error Flag This bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Invalid frame type has not been received. 1h[R] = Invalid frame type has been received To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
2 | CRC_ERR | R | 0h | CRC Error Flag This bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = CRC error has not occured. 1h[R] = CRC error has occured. To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
1 | FRAME_WD_TO | R | 0h | Frame Watchdog Timeout Flag This bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Frame watchdog timeout has not occured. 1h[R] = Frame watchdog timeout has occured. To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
0 | PING_WD_TO | R | 0h | Ping Watchdog Timeout Flag This bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by Writing to the RX_EVT_FRC register. 0h[R] = Ping watchdog timeout has not occured. 1h[R] = Ping watchdog timeout has occured. To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |