SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Receive interrupt control register for RX_INT1.
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| Instance Name | Physical Address |
|---|---|
| FSI_RX0 | 5029 0038h |
| FSI_RX1 | 5029 1038h |
| FSI_RX2 | 502B 0038h |
| FSI_RX3 | 502B 1038h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_1 | INT1_EN_ERROR_TAG_MATCH | INT1_EN_DATA_TAG_MATCH | INT1_EN_PING_TAG_MATCH | INT1_EN_DATA_FRAME | INT1_EN_FRAME_OVERRUN | INT1_EN_PING_FRAME | INT1_EN_ERR_FRAME |
| R | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INT1_EN_UNDERRUN | INT1_EN_FRAME_DONE | INT1_EN_OVERRUN | INT1_EN_EOF_ERR | INT1_EN_TYPE_ERR | INT1_EN_CRC_ERR | INT1_EN_FRAME_WD_TO | INT1_EN_PING_WD_TO |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED_1 | R | 0h | Reserved |
| 14 | INT1_EN_ERROR_TAG_MATCH | R/W | 0h | Enable Error Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = An error frame received with matching tag will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
| 13 | INT1_EN_DATA_TAG_MATCH | R/W | 0h | Enable Data Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A data frame received with matching tag will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
| 12 | INT1_EN_PING_TAG_MATCH | R/W | 0h | Enable Ping Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A ping frame received with matching tag will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
| 11 | INT1_EN_DATA_FRAME | R/W | 0h | Enable Data Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A data frame received event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
| 10 | INT1_EN_FRAME_OVERRUN | R/W | 0h | Enable Frame Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A frame overrun event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
| 9 | INT1_EN_PING_FRAME | R/W | 0h | Enable Ping Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A ping frame received event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
| 8 | INT1_EN_ERR_FRAME | R/W | 0h | Enable ERROR Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A error frame received event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
| 7 | INT1_EN_UNDERRUN | R/W | 0h | Enable Buffer Underrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A buffer underrun event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
| 6 | INT1_EN_FRAME_DONE | R/W | 0h | Enable Frame Done Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A frame done event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
| 5 | INT1_EN_OVERRUN | R/W | 0h | Enable Receive Buffer Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A receive buffer overrun event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
| 4 | INT1_EN_EOF_ERR | R/W | 0h | Enable End-of-Frame Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = An end-of-frame error event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
| 3 | INT1_EN_TYPE_ERR | R/W | 0h | Enable Frame Type Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A frame type error event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
| 2 | INT1_EN_CRC_ERR | R/W | 0h | Enable CRC Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A CRC error will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
| 1 | INT1_EN_FRAME_WD_TO | R/W | 0h | Enable Frame Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A frame watchdog timeout event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
| 0 | INT1_EN_PING_WD_TO | R/W | 0h | Enable Ping Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event. 0h[R/W] = This event will not trigger an interrupt on RX_INT1. 1h[R/W] = A ping watchdog timeout event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |