SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Receive Trigger Control register 0
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Instance Name | Physical Address |
---|---|
FSI_RX0 | 5029 0058h |
FSI_RX1 | 5029 1058h |
FSI_RX2 | 502B 0058h |
FSI_RX3 | 502B 1058h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RX_TRIG_DLY | |||||||
R/W | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RX_TRIG_DLY | |||||||
R/W | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RX_TRIG_DLY | |||||||
R/W | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | TRIG_SEL | TRIG_EN | |||||
R | R/W | R/W | |||||
0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:8 | RX_TRIG_DLY | R/W | 0h | This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled, the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined by this 24-bt value. |
7:5 | RESERVED_1 | R | 0h | Reserved |
4:1 | TRIG_SEL | R/W | 0h | This is the mux Select Value which selects which of the inputs will be used as the trigger source. |
0 | TRIG_EN | R/W | 0h | This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0, then no trigger will be generated by this module. |