SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

9.2.30.1 FSI_RX_CFG_RX_DLYLINE_CTRL Register (Offset = 60h) [reset = 0h]

Receive delay line control register.

Table 3-1052 Instance Table

Figure 3-495 FSI_RX_CFG_RX_DLYLINE_CTRL Name Register

Table 3-1053 FSI_RX_CFG_RX_DLYLINE_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED_1	R	0h	Reserved
14:10	RXD1_DLY	R/W	0h	Delay Line Tap Select for RXD1 This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXD1 path. RXD1 is taken directly from the pin. 1h[R/W] One delay element is included in the RXD1 path. 2h[R/W] Two delay elements are included in the RXD1 path. ... 1Fh [R/W] 31 delay elements are included in the RXD1 path, the maximum.
9:5	RXD0_DLY	R/W	0h	Delay Line Tap Select for RXD0 This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXD0 path. RXD0 is taken directly from the pin. 1h[R/W] One delay element is included in the RXD0 path. 2h[R/W] Two delay elements are included in the RXD0 path. ... 1Fh [R/W] 31 delay elements are included in the RXD0 path, the maximum.
4:0	RXCLK_DLY	R/W	0h	Delay Line Tap Select for RXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the RXCLK path. RXCLK is taken directly from the pin. 1h[R/W] One delay element is included in the RXCLK path. 2h[R/W] Two delay elements are included in the RXCLK path. ... 1Fh [R/W] 31 delay elements are included in the RXCLK path, the maximum.