SPRUJ42 User guide | TI.com

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.10.2.16 I2C_ICDMAC Register

10.2.16.1 I2C_ICDMAC Register (Offset = 3Ch) [reset = 0h]

I2C DMA Control Register

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Table 5-1270 Instance Table

Instance Name	Physical Address
I2C0	5250 003Ch
I2C1	5250 103Ch
I2C2	5250 203Ch
I2C3	5250 303Ch

Figure 5-629 I2C_ICDMAC Name Register

31	30	29	28	27	26	25	24
NU
R/W
0h
23	22	21	20	19	18	17	16
NU
R/W
0h
15	14	13	12	11	10	9	8
NU
R/W
0h
7	6	5	4	3	2	1	0
NU						TXDMAEN	RXDMAEN
R/W						R/W	R/W
0h						0h	0h

Table 5-1271 I2C_ICDMAC Register Field Descriptions

Bit	Field	Type	Reset	Description
31:2	NU	R/W	0h	Reserved. - [RW ]
1	TXDMAEN	R/W	0h	Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never asserted. RXDMAEN 0:DMA transmit event is disabled. RXDMAEN 1:DMA transmit event is enabled. [Default]
0	RXDMAEN	R/W	0h	Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never asserted. RXDMAEN 0:DMA receive event is disabled. RXDMAEN 1:DMA receive event is enabled. [Default]