SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

10.2.24.1 I2C_ICPDCLR Register (Offset = 5Ch) [reset = 0h]

I2C Pin Data Clear register

Table 5-1286 Instance Table

Figure 5-637 I2C_ICPDCLR Name Register

Table 5-1287 I2C_ICPDCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31:2	NU	R/W	0h	Reserved
1	PDCLR1	R/W	0h	Used to clear PDOUT[1] bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is cleared to logic low.
0	PDCLR0	R/W	0h	Used to clear PDOUT[0] bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is cleared to logic low.