SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Self test Global control Reg0. *NOT BYTE ACCESSIBLE.
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Instance Name | Physical Address |
---|---|
R5SS0 | 5350 0000h |
R5SS1 | 5351 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
INTCOUNT_B16 | |||||||
R/W | |||||||
1h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INTCOUNT_B16 | |||||||
R/W | |||||||
1h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NU0 | CAP_IDLE_CYCLE | ||||||
R | R/W | ||||||
0h | 1h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCANEN_HIGH_CAP_IDLE_CYCLE | NU1 | RS_CNT_B1 | |||||
R/W | NU1 | R/W | |||||
1h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:16 | INTCOUNT_B16 | R/W | 1h | Number of intervals of the self test run [RWP - Read, Priviledge Mode Write only] Count of intervals that need to be covered for a specific selftest run. The selftest controller sends out complete indication once it runs all of the intervals programmed in this field. INTCOUNT_B16=0 is an invalid configuration for a selftest. |
15:11 | NU0 | R | 0h | Reserved bits |
10:8 | CAP_IDLE_CYCLE | R/W | 1h | Idle cycles before and after capture clock [RWP - Read, Priviledge Mode Write only] Idle Cycles before and after capture clock. This value is used to insert that many idle cycles in the Capture phase. Programmable idle cycles allow implementation flexibility on SCAN_EN signal at chip level based on the size of the UUT and timing requirements. |
7:5 | SCANEN_HIGH_CAP_IDLE_CYCLE | R/W | 1h | Idle cycles before and after capture clock [RWP - Read, Priviledge Mode Write only]. *NOT BYTE ACCESSIBLE Idle Cycles between scan_en going high to func_clk_en generation and scan_en going high to misr_log_en generation. This value is used to insert that many idle cycles in the shift clock [scan_en going high to func_clk_en generation] and misr_log_clk [scan_en going high to misr_log_en generation] generation. Programmable idle cycles allow implementation flexibility on SCAN_EN signal at chip level based on the size of the UUT and timing requirements. |
4:2 | NU1 | NU1 | 0h | Reserved bits |
1:0 | RS_CNT_B1 | R/W | 0h | Restart/Continue or preload [RWP - Read, Priviledge Mode Write only] This bit specifies the selftest controller whether to continue the run from next interval onwards, restart from ROM address 0 or preload from a prescribed interval. This bit gets reset after the completion of selftest run. 00 = Continue NSTC run from previous interval 01 = Restart NSTC run from ROM address 0 1X = Start from segment number specified in STC_SEGPLR register |