SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Clock Divider Register.
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Instance Name | Physical Address |
---|---|
R5SS0 | 5350 0024h |
R5SS1 | 5351 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NU8 | CLKDIV0 | ||||||
R | R/W | ||||||
0h | 0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NU9 | CLKDIV1 | ||||||
R | R/W | ||||||
0h | 0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NU10 | CLKDIV2 | ||||||
R | R/W | ||||||
0h | 0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NU11 | CLKDIV3 | ||||||
R | R/W | ||||||
0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:27 | NU8 | R | 0h | Reserved bits |
26:24 | CLKDIV0 | R/W | 0h | Clock division for Seg0 [RWP - Read, Priviledge Mode Write only] *NOT SUPPORTED X = Division ratio is X+1 for Segment 0 |
23:19 | NU9 | R | 0h | Reserved bits |
18:16 | CLKDIV1 | R/W | 0h | Clock division for Seg1 [RWP - Read, Priviledge Mode Write only] *NOT SUPPORTED X = Division ratio is X+1 for Segment 1 |
15:11 | NU10 | R | 0h | Reserved bits |
10:8 | CLKDIV2 | R/W | 0h | Clock division for Seg2 [RWP - Read, Priviledge Mode Write only] *NOT SUPPORTED X = Division ratio is X+1 for Segment 2 |
7:3 | NU11 | R | 0h | Reserved bits |
2:0 | CLKDIV3 | R/W | 0h | Clock division for Seg3 [RWP - Read, Priviledge Mode Write only] *NOT SUPPORTED X = Division ratio is X+1 for Segment 3 |