SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
ROM Start address for Segment0.
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Instance Name | Physical Address |
---|---|
R5SS0 | 5350 002Ch |
R5SS1 | 5351 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
NU13 | |||||||
R | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NU13 | SEG_START_ADDR | ||||||
R | R/W | ||||||
0h | 0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEG_START_ADDR | |||||||
R/W | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEG_START_ADDR | |||||||
R/W | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:20 | NU13 | R | 0h | Reserved bits |
19:0 | SEG_START_ADDR | R/W | 0h | Segment 0 Start Address [RWP - Read, Priviledge Mode Write only] This register holds the ROM address for the start of first interval of the segment. When STC_GCR0.RS_CNT_B1 field is set to [1x] PRELOAD option, this register is used to determine the ROM start address for the Segment selected in ST_SEGPLR register. Valid number of bits depends on RTL paramerter ADDR |