SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Holds the MISR signature for CORE1.
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Instance Name | Physical Address |
---|---|
R5SS0 | 5350 004Ch |
R5SS1 | 5351 004Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
C1MISR4 | |||||||
R | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
C1MISR4 | |||||||
R | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
C1MISR4 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
C1MISR4 | |||||||
R | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:0 | C1MISR4 | R | 0h | MISR Signature for CORE1 This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its default value with Power on or system reset assertion. The MISR values should be read only after the Self Test is completed. |