SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
THost Threshold Pulse Interrupt Status Register
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Instance Name | Physical Address |
---|---|
CPSW0 | 5280 18D0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_THRESH_PULSE_STATUS | |||||||
R | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:8 | RESERVED | NONE | 0h | Reserved |
7:0 | TH_THRESH_PULSE_STATUS | R | 0h | Core 3 THost Threshold Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the THost threshold interrupt that is enabled and generating an interrupt on C3_TH_THRESH_PULSE. |