SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.1.2.71 CPSW_NC_CONTROL_REG Register

1.2.71.1 CPSW_NC_CONTROL_REG Register (Offset = 20004h) [reset = 0h]

CPSW Switch Control

Table 5-142 Instance Table

Instance Name	Physical Address
CPSW0	5282 0004h

Figure 5-71 CPSW_NC_CONTROL_REG Name Register

31	30	29	28	27	26	25	24
ECC_CRC_MODE	RESERVED
R/W	NONE
0h	0h
23	22	21	20	19	18	17	16
RESERVED					EST_ENABLE	RESERVED	EEE_ENABLE
NONE					R/W	R/W	R/W
0h					0h	0h	0h
15	14	13	12	11	10	9	8
P0_FH_PASS_CRC_ERR	P0_FH_PAD	P0_TH_CRC_REMOVE	RESERVED	P8_PASS_PRI_TAGGED	P7_PASS_PRI_TAGGED	P6_PASS_PRI_TAGGED	P5_PASS_PRI_TAGGED
R/W	R/W	R/W	NONE	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
P4_PASS_PRI_TAGGED	P3_PASS_PRI_TAGGED	P2_PASS_PRI_TAGGED	P1_PASS_PRI_TAGGED	P0_PASS_PRI_TAGGED	P0_ENABLE	VLAN_AWARE	S_CN_SWITCH
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 5-143 CPSW_NC_CONTROL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	ECC_CRC_MODE	R/W	0h	ECC CRC Mode - 0 - ECC errors induced through the ECC aggregator flip bits in the packet headers (not in packet data). 1 - ECC errors induced through the ECC aggregator flip bits in the packet data (not in the packet headers).
30:19	RESERVED	NONE	0h	Reserved
18	EST_ENABLE	R/W	0h	Enhanced Scheduled Traffic enable (EST) - 0 - EST is disabled. 1 - EST is enabled
17	RESERVED	R/W	0h	RESERVED
16	EEE_ENABLE	R/W	0h	Energy Efficient Ethernet enable - 0 - Energy Efficient Ethernet is disabled. 1 - Energy Efficient Ethernet is enabled.
15	P0_FH_PASS_CRC_ERR	R/W	0h	Port 0 Pass Received CRC errors - 0 - Packets received with CRC errors on port 0 are dropped. 1 - Packets received with CRC errors on port 0 are transferred to the destination ports.
14	P0_FH_PAD	R/W	0h	Port 0 Receive Short Packet Pad - 0 - short packets are dropped. 1 - short packets are padded to 64-bytes (with pad and added CRC) if the CRC is not passed in. Short packets are dropped if the CRC is passed (in the Info0 word).
13	P0_TH_CRC_REMOVE	R/W	0h	Port 0 Transmit CRC remove - 0 - Do not remove the CRC on Port 0 THost (egress) packets. 1 - Remove the CRC on all Port 0 THost (egress) packets.
12	RESERVED	NONE	0h	Reserved
11	P8_PASS_PRI_TAGGED	R/W	0h	Port 8 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P8_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged.
10	P7_PASS_PRI_TAGGED	R/W	0h	Port 7 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P7_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged.
9	P6_PASS_PRI_TAGGED	R/W	0h	Port 6 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P6_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged.
8	P5_PASS_PRI_TAGGED	R/W	0h	Port 5 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P5_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged.
7	P4_PASS_PRI_TAGGED	R/W	0h	Port 4 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P4_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged.
6	P3_PASS_PRI_TAGGED	R/W	0h	Port 3 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P3_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged.
5	P2_PASS_PRI_TAGGED	R/W	0h	Port 2 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P2_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged.
4	P1_PASS_PRI_TAGGED	R/W	0h	Port 1 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P1_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged.
3	P0_PASS_PRI_TAGGED	R/W	0h	Port 0 Pass Priority Tagged - 0 - Priority tagged packets have the zero VID replaced with the input port Enet_P0_PORT_VLAN[11:0] on ingress. 1 - Priority tagged packets are processed unchanged.
2	P0_ENABLE	R/W	0h	Port 0 Enable - 0 - Port 0 is disabled 1 - Port 0 is enabled
1	VLAN_AWARE	R/W	0h	VLAN Aware Mode - 0 - CPSW_NU is in the VLAN unaware mode. 1 - CPSW_NU is in the VLAN aware mode.
0	S_CN_SWITCH	R/W	0h	Service or Customer VLAN switch. 0 - Customer switch. VLAN processing uses the inner_vlan_ltype. 1 - Service switch. VLAN processing uses the outer_vlan_ltype.