SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.1.2.156 CPSW_NC_ETH_MAC_PN_MAC_CONTROL_REG_K Register

1.2.156.1 CPSW_NC_ETH_MAC_PN_MAC_CONTROL_REG_K Register (Offset = 22330h) [reset = 0h]

Enet Port N Mac Control

Offset = Base + (k * 1000h); where k = 0 to 1d

Table 5-312 Instance Table

Instance Name	Physical Address
CPSW0	5282 2330h + formula

Figure 5-156 CPSW_NC_ETH_MAC_PN_MAC_CONTROL_REG_K Name Register

31	30	29	28	27	26	25	24
RESERVED							RX_CMF_EN
NONE							R/W
0h							0h
23	22	21	20	19	18	17	16
RX_CSF_EN	RX_CEF_EN	TX_SHORT_GAP_LIM_EN	EXT_TX_FLOW_EN	EXT_RX_FLOW_EN	EXT_EN	GIG_FORCE	IFCTL_B
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
IFCTL_A	RESERVED		CRC_TYPE	CMD_IDLE	TX_SHORT_GAP_ENABLE	RESERVED
R/W	NONE		R/W	R/W	R/W	NONE
0h	0h		0h	0h	0h	0h
7	6	5	4	3	2	1	0
GIG	TX_PACE	GMII_EN	TX_FLOW_EN	RX_FLOW_EN	MTEST	LOOPBACK	FULLDUPLEX
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 5-313 CPSW_NC_ETH_MAC_PN_MAC_CONTROL_REG_K Register Field Descriptions

Bit	Field	Type	Reset	Description
31:25	RESERVED	NONE	0h	Reserved
24	RX_CMF_EN	R/W	0h	RX Copy MAC Control Frames Enable - Enables MAC control frames to be transferred to memory. MAC control frames are normally acted upon (if enabled), but not copied/transferred to memory. MAC control frames that are pause frames will be acted upon if enabled in the MacControl register, regardless of the value of pn_rx_cmf_en. Frames transferred to memory due to pn_rx_cmf_en will have the mac_control bit set in their EOP buffer descriptor. 0 - MAC control frames are filtered (but are acted upon if enabled). 1 - MAC control frames are transferred to the host.
23	RX_CSF_EN	R/W	0h	RX Copy Short Frames Enable - Enables frames or fragments shorter than 64 bytes to be sent to the host. Frames transferred to the host due to pn_rx_csf_en will have the fragment or undersized bit set in their buffer descriptor. Short and fragment frame transfer is not guaranteed for all packet conditions and is best case only. Frames shorter than 33 bytes will be dropped in all cases. Fragments are short frames that contain CRC/align/code errors and undersized are short frames without errors. The pn_rx_cef_en bit must also be set to transfer fragment frames. 0 - Short frames are filtered. 1 - Short frames are transferred to the host.
22	RX_CEF_EN	R/W	0h	RX Copy Error Frames Enable - Enables frames containing errors to be transferred to memory. The appropriate error bit will be set in the frame receive buffer descriptor. Frames containing errors will be filtered when this bit is not set. 0 - Frames containing errors are filtered. 1 - Frames containing errors are transferred to the host.
21	TX_SHORT_GAP_LIM_EN	R/W	0h	Transmit Short Gap Limit Enable - When set this bit limits the number of short gap packets transmitted to 100ppm. The pn_tx_short_gap_en bit must also be set. Each time a short gap packet is sent, a counter is loaded with 10,000 and decremented on each wireside clock. Another short gap packet will not be sent out until the counter decrements to zero. This mode is included to preclude the host from filling up the FIFO and sending every packet out with short gap which would violate the maximum number of packets per second allowed. This bit is used only with GMII (not XGMII).
20	EXT_TX_FLOW_EN	R/W	0h	External Transmit Flow Control Enable - Enables the pn_tx_flow_en to be selected from the EXT_TX_FLOW_EN input signal and not from the pn_tx_flow_en bit in this register.
19	EXT_RX_FLOW_EN	R/W	0h	External Receive Flow Control Enable - Enables the pn_rx_flow_en to be selected from the EXT_RX_FLOW_EN input signal and not from the pn_rx_flow_en bit in this register.
18	EXT_EN	R/W	0h	External Control Enable - Enables the fullduplex and gigabit mode to be selected from the FULLDUPLEX_IN and GIG_IN input signals and not from the pn_fullduplex and pn_gig bits in this register. The FULLDUPLEX_MODE bit reflects the actual fullduplex mode selected.
17	GIG_FORCE	R/W	0h	Gigabit Mode Force - This bit is used to force the Enet Mac into gigabit mode if the input GMII_MTCLK has been stopped by the PHY. 0 - GIG mode not forced 1 - GIG mode forced regardless of transmit clock
16	IFCTL_B	R/W	0h	Interface Control B - Intended as a general purpose output bit to be used to control external gaskets associated with the GMII (GMII to RGMII etc).
15	IFCTL_A	R/W	0h	Interface Control A - Intended as a general purpose output bit to be used to control external gaskets associated with the GMII (GMII to RGMII etc).
14:13	RESERVED	NONE	0h	Reserved
12	CRC_TYPE	R/W	0h	Port CRC Type - 0 - Ethernet CRC. 1 - Castagnoli CRC.
11	CMD_IDLE	R/W	0h	Command Idle - 0 - Idle not commanded. 1 - Idle Commanded (read pn_idle in Enet_Pn_Mac_Status).
10	TX_SHORT_GAP_ENABLE	R/W	0h	Transmit Short Gap Enable 0 - Transmit with a short IPG is disabled. 1 - Transmit with a short IPG is enabled.
9:8	RESERVED	NONE	0h	Reserved
7	GIG	R/W	0h	Gigabit Mode - 0 - 10/100 mode. 1 - Gigabit mode (full duplex only) The GIG_OUT output is the value of this bit. This bit is a don't care when pn_xgig is set.
6	TX_PACE	R/W	0h	Transmit Pacing Enable - 0 - Transmit Pacing Disabled. 1 - Transmit Pacing Enabled
5	GMII_EN	R/W	0h	GMII Enable - 0 - GMII RX and TX held in reset. 1 - GMII RX and TX released from reset. This bit should be written with a logic high before the other bits in this register are written.
4	TX_FLOW_EN	R/W	0h	Transmit Flow Control Enable - Determines if incoming pause frames are acted upon in full-duplex mode. Incoming pause frames are not acted upon in half-duplex mode regardless of this bit setting. The RX_MBP_Enable bits determine whether or not received pause frames are transferred to memory. 0 - Transmit Flow Control Disabled. Full-duplex mode - Incoming pause frames are not acted upon. 1 - Transmit Flow Control Enabled . Full-duplex mode - Incoming pause frames are acted upon.
3	RX_FLOW_EN	R/W	0h	Receive Flow Control Enable - 0 - Receive Flow Control Disabled: Half-duplex mode - No flow control generated collisions are sent. Full-duplex mode - No outgoing pause frames are sent. 1 - Receive Flow Control Enabled: Half-duplex mode - Collisions are initiated when receive flow control is triggered. Full-duplex mode - Outgoing pause frames are sent when receive flow control is triggered.
2	MTEST	R/W	0h	Manufacturing Test mode - This bit must be set to allow writes to the Backoff_Test and PauseTimer registers.
1	LOOPBACK	R/W	0h	Loop Back Mode - Loopback mode forces internal fullduplex mode regardless of whether the pn_fullduplex bit is set or not. The pn_loopback bit should be changed only when pn_gmii_en is de-asserted. Loopback is used only with GMII (not XGMII). Loopback is not compatible with timestamp operations (CPTS). 0 - Loop Back Mode disabled. 1 - Loop Back Mode enabled.
0	FULLDUPLEX	R/W	0h	Full Duplex mode - Gigabit mode forces fullduplex mode regardless of whether the pn_fullduplex bit is set or not. The FULLDUPLEX_OUT output is the value of this register bit. 0 - half duplex mode. 1 - full duplex mode.