SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.1.2.157 CPSW_NC_ETH_MAC_PN_MAC_STATUS_REG_K Register

1.2.157.1 CPSW_NC_ETH_MAC_PN_MAC_STATUS_REG_K Register (Offset = 22334h) [reset = D0000000h]

Enet Port N Mac Status

Offset = Base + (k * 1000h); where k = 0 to 1d

Table 5-314 Instance Table

Instance Name	Physical Address
CPSW0	5282 2334h + formula

Figure 5-157 CPSW_NC_ETH_MAC_PN_MAC_STATUS_REG_K Name Register

31	30	29	28	27	26	25	24
IDLE	E_IDLE	RESERVED	MAC_TX_IDLE	TORF	TORF_PRI
R	R	NONE	R	R	R
1h	1h	0h	1h	0h	0h
23	22	21	20	19	18	17	16
TX_PFC_FLOW_ACT
R
0h
15	14	13	12	11	10	9	8
RX_PFC_FLOW_ACT
R
0h
7	6	5	4	3	2	1	0
RESERVED	EXT_TX_FLOW_EN	EXT_RX_FLOW_EN	EXT_GIG	EXT_FULLDUPLEX	RESERVED	RX_FLOW_ACT	TX_FLOW_ACT
NONE	R	R	R	R	NONE	R	R
0h	0h	0h	0h	0h	0h	0h	0h

Table 5-315 CPSW_NC_ETH_MAC_PN_MAC_STATUS_REG_K Register Field Descriptions

Bit	Field	Type	Reset	Description
31	IDLE	R	1h	Enet IDLE - The Ethernet port (express and prempt) is in the idle state when high.
30	E_IDLE	R	1h	Express MAC is idle when high
29	RESERVED	NONE	0h	Reserved
28	MAC_TX_IDLE	R	1h	Mac Transmit Idle - Both Prempt (if iet_incl) and Express MAC Transmit are in idle state.The transmit clock must be running for this to go idle.
27	TORF	R	0h	Top of receive FIFO flow control trigger occurred. This bit is write one to clear.
26:24	TORF_PRI	R	0h	The lowest priority that caused top of receive FIFO flow control trigger since the last write to clear. This field is write 0x7 to clear.
23:16	TX_PFC_FLOW_ACT	R	0h	Receive Priority Based Flow Control Active (priority 7 down to 0).
15:8	RX_PFC_FLOW_ACT	R	0h	Transmit Priority Based Flow Control Active (priority 7 down to 0).
7	RESERVED	NONE	0h	Reserved
6	EXT_TX_FLOW_EN	R	0h	External Transmit Flow Control Enable - This is the value of the EXT_TX_FLOW_EN input bit.
5	EXT_RX_FLOW_EN	R	0h	External Receive Flow Control Enable - This is the value of the EXT_RX_FLOW_EN input bit.
4	EXT_GIG	R	0h	External GIG - This is the value of the EXT_GIG input bit.
3	EXT_FULLDUPLEX	R	0h	External Fullduplex - This is the value of the EXT_FULLDUPLEX input bit.
2	RESERVED	NONE	0h	Reserved
1	RX_FLOW_ACT	R	0h	Receive Flow Control Active - When asserted, indicates that receive flow control is enabled and triggered.
0	TX_FLOW_ACT	R	0h	Transmit Flow Control Active - When asserted, this bit indicates that the pause time period is being observed for a received pause frame. No new transmissions will begin while this bit is asserted except for the transmission of pause frames. Any transmission in progress when this bit is asserted will complete.