SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.1.2.341 CPSW_NC_CPTS_CONTROL_REG Register

1.2.341.1 CPSW_NC_CPTS_CONTROL_REG Register (Offset = 3D004h) [reset = 4h]

Time Sync Control Register

Table 5-682 Instance Table

Instance Name	Physical Address
CPSW0	5283 D004h

Figure 5-341 CPSW_NC_CPTS_CONTROL_REG Name Register

31	30	29	28	27	26	25	24
TS_SYNC_SEL				RESERVED
R/W				NONE
0h				0h
23	22	21	20	19	18	17	16
RESERVED						TS_GENF_CLR_EN	TS_RX_NO_EVENT
NONE						R/W	R/W
0h						0h	0h
15	14	13	12	11	10	9	8
HW8_TS_PUSH_EN	HW7_TS_PUSH_EN	HW6_TS_PUSH_EN	HW5_TS_PUSH_EN	HW4_TS_PUSH_EN	HW3_TS_PUSH_EN	HW2_TS_PUSH_EN	HW1_TS_PUSH_EN
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
TS_PPM_DIR	TS_COMP_TOG	MODE	SEQUENCE_EN	TSTAMP_EN	TS_COMP_POLARITY	INT_TEST	CPTS_EN
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	1h	0h	0h

Table 5-683 CPSW_NC_CPTS_CONTROL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31:28	TS_SYNC_SEL	R/W	0h	TS_SYNC output timestamp counter bit select - 0000 - TS_SYNC disabled. 0001 - TS_SYNC is timestamp counter bit 17 0010 - TS_SYNC is timestamp counter bit 18 ... 1110 - TS_SYNC is timestamp counter bit 30 1111 - TS_SYNC is timestamp counter bit 31
27:18	RESERVED	NONE	0h	Reserved
17	TS_GENF_CLR_EN	R/W	0h	GENF (and ESTF) Clear Enable - 0 - A TS_GENFn output is not cleared when the associated ts_genf_length[31:0] is cleared to zero. 1 - A TS_GENFn output is cleared when the associated ts_genf_length[31:0] is cleared to zero.
16	TS_RX_NO_EVENT	R/W	0h	Timestamp Ethernet Receive produces no events - 0 - Ethernet receive timesync events enabled. 1 - Ethernet receive timesync events disabled.
15	HW8_TS_PUSH_EN	R/W	0h	Hardware push 8 enable
14	HW7_TS_PUSH_EN	R/W	0h	Hardware push 7 enable
13	HW6_TS_PUSH_EN	R/W	0h	Hardware push 6 enable
12	HW5_TS_PUSH_EN	R/W	0h	Hardware push 5 enable
11	HW4_TS_PUSH_EN	R/W	0h	Hardware push 4 enable
10	HW3_TS_PUSH_EN	R/W	0h	Hardware push 3 enable
9	HW2_TS_PUSH_EN	R/W	0h	Hardware push 2 enable
8	HW1_TS_PUSH_EN	R/W	0h	Hardware push 1 enable
7	TS_PPM_DIR	R/W	0h	PPM Correction Direction - 0 - Increase the time_stamp[63:0] value by the PPM value. 1 - Decrease the time_stamp[63:0] value by the PPM value.
6	TS_COMP_TOG	R/W	0h	Timestamp Compare Toggle mode - 0 - TS_COMP is in non-toggle mode. 1 - TS_COMP is in toggle mode.
5	MODE	R/W	0h	64-Bit Mode - 0 - The timestamp is 32-bits with the upper 32-bits forced to zero. 1 - The timestamp is 64-bits.
4	SEQUENCE_EN	R/W	0h	Sequence Enable - 0 - The timestamp value increments with the selected RFTCLK (normal operation). 1 - The timestamp for received packets is the sequence number of the received packet (first packet is 1, second packet is 2, etc). This can be used for test purposes.
3	TSTAMP_EN	R/W	0h	Host Receive Timestamp Enable - 0 - Timestamps are disabled on received packets to host. 1 - Timestamps enabled on received packets to host (cpts_en must be set).
2	TS_COMP_POLARITY	R/W	1h	TS_COMP Polarity 0 - TS_COMP is asserted low 1 - TS_COMP is asserted high
1	INT_TEST	R/W	0h	Interrupt Test - When set, this bit allows the raw interrupt to be written to facilitate interrupt test.
0	CPTS_EN	R/W	0h	Time Sync Enable - When disabled (cleared to zero), the CPTS RCLK domain is held in reset.