SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

1.2.343.1 CPSW_NC_CPTS_TS_PUSH_REG Register (Offset = 3D00Ch) [reset = 0h]

Time Stamp Event Push Register

Table 5-686 Instance Table

Instance Name	Physical Address
CPSW0	5283 D00Ch

Figure 5-343 CPSW_NC_CPTS_TS_PUSH_REG Name Register

Table 5-687 CPSW_NC_CPTS_TS_PUSH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31:1	RESERVED	NONE	0h	Reserved
0	TS_PUSH	W	0h	Time stamp event push - When a logic high is written to this bit a time stamp event is pushed onto the event FIFO. The time stamp value is the time of the write of this register, not the time of the event read. The time stamp value can then be read on interrupt via the event registers. Software should not push a second time stamp event onto the event FIFO until the first time stamp value has been read from the event FIFO (there should be only one time stamp event in the event FIFO at any given time). This bit is write only and always reads zero.