SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.1.2.403 CPSW_NC_ALE_POLICECFG6 Register

1.2.403.1 CPSW_NC_ALE_POLICECFG6 Register (Offset = 3E118h) [reset = 0h]

The PIR counter is a 37 bit internal counter where ~ipir_idle_inc_val is added every clock and the frame size << 18 is subtracted at EOF if not RED at LUT time. If the counter is negative the packet will be marked RED, else it can be YELLOW or GREEN based on the CIR counter. If only this counter is used (aka cir_idle_inc_val==0) Packet are marked RED or GREEN based on PIR counter only.

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Table 5-806 Instance Table

Instance Name	Physical Address
CPSW0	5283 E118h

Figure 5-403 CPSW_NC_ALE_POLICECFG6 Name Register

31	30	29	28	27	26	25	24
PIR_IDLE_INC_VAL
R/W
0h
23	22	21	20	19	18	17	16
PIR_IDLE_INC_VAL
R/W
0h
15	14	13	12	11	10	9	8
PIR_IDLE_INC_VAL
R/W
0h
7	6	5	4	3	2	1	0
PIR_IDLE_INC_VAL
R/W
0h

Table 5-807 CPSW_NC_ALE_POLICECFG6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31:0	PIR_IDLE_INC_VAL	R/W	0h	Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle. If zero the PIR counter is disabled and packets will never be marked or processed as RED.