SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

4.2.2.203 ICSSM_PR1_ICSS_UART_UART_SLV_RBR Register

2.2.203.1 ICSSM_PR1_ICSS_UART_UART_SLV_RBR Register (Offset = 0h) [reset = 0h]

Receiver Buffer Register (read only)
The UART receiver section consists of a receiver shift register (RSR) and a receiver buffer register (RBR). When the UART is in the FIFO mode, RBR is a 16-byte FIFO. Timing is supplied by the 16x receiver clock or 13x receiver clock by programming OSM_SEL bit field of MDR register. Receiver section control is a function of the line control register (LCR).
RSR receives serial data from the UARTn_RXD pin. Then RSR concatenates the data and moves it into RBR (or the receiver FIFO). In the non-FIFO mode, when a character is placed in RBR and the receiver data-ready interrupt is enabled (DR = 1 in IER), an interrupt is generated. This interrupt is cleared when the character is read from RBR. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger level selected in the FIFO control register (FCR), and it is cleared when the FIFO contents drop below the trigger level.

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Table 4-827 Instance Table

Instance Name	Physical Address
ICSSM0	4802 8000h

Figure 4-397 ICSSM_PR1_ICSS_UART_UART_SLV_RBR Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED						RESERVED
NONE						W
0h						0h
15	14	13	12	11	10	9	8
RESERVED
W
0h
7	6	5	4	3	2	1	0
DATA
R
0h

Table 4-828 ICSSM_PR1_ICSS_UART_UART_SLV_RBR Register Field Descriptions

Bit	Field	Type	Reset	Description
31:18	RESERVED	NONE	0h	Reserved
17:8	RESERVED	W	0h	Reserved
7:0	DATA	R	0h	Received Data