SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.14.2.11 MCSPI_CH0CONF Register

14.2.11.1 MCSPI_CH0CONF Register (Offset = 12Ch) [reset = 60000h]

This register is dedicated to the configuration of the channel 0

Table 5-1717 Instance Table

Instance Name	Physical Address
MCSPI0	5220 012Ch
MCSPI1	5220 112Ch
MCSPI2	5220 212Ch
MCSPI3	5220 312Ch
MCSPI4	5220 412Ch

Figure 5-847 MCSPI_CH0CONF Name Register

31	30	29	28	27	26	25	24
RESERVED_0		CLKG	FFER	FFEW	TCS0		SBPOL
R		R/W	R/W	R/W	R/W		R/W
0h		0h	0h	0h	0h		0h
23	22	21	20	19	18	17	16
SBE	SPIENSLV		FORCE	TURBO	IS	DPE1	DPE0
R/W	R/W		R/W	R/W	R/W	R/W	R/W
0h	0h		0h	0h	1h	1h	0h
15	14	13	12	11	10	9	8
DMAR	DMAW	TRM		WL
R/W	R/W	R/W		R/W
0h	0h	0h		0h
7	6	5	4	3	2	1	0
WL	EPOL	CLKD				POL	PHA
R/W	R/W	R/W				R/W	R/W
0h	0h	0h				0h	0h

Table 5-1718 MCSPI_CH0CONF Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	RESERVED_0	R	0h	Read returns 0
29	CLKG	R/W	0h	Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values 1 One clock cycle granularity 0 Clock granularity of power of 2
28	FFER	R/W	0h	FIFO enabled for receive:Only one channel can have this bit field set 1 The buffer is used to receive data. 0 The buffer is not used to receive data.
27	FFEW	R/W	0h	FIFO enabled for Transmit:Only one channel can have this bit field set 1 The buffer is used to transmit data. 0 The buffer is not used to transmit data.
26:25	TCS0	R/W	0h	Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 3 3.5 clock cycles 2 2.5 clock cycles 1 1.5 clock cycles 0 0.5 clock cycle
24	SBPOL	R/W	0h	Start bit polarity 1 SPICLK is held high during the INACTIVE state 0 SPICLK is held low during the INACTIVE state
23	SBE	R/W	0h	Start bit enable for SPI transfer 1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL 0 Default MCSPI transfer length as specified by WL bit field
22:21	SPIENSLV	R/W	0h	Channel 0 only and target mode only: SPI target select signal detection Reserved bits for other cases 3 Detection enabled only on SPIEN[3] 2 Detection enabled only on SPIEN[2] 1 Detection enabled only on SPIEN[1] 0 Detection enabled only on SPIEN[0]
20	FORCE	R/W	0h	Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] 1 Writing 1 into this bit drives high the SPIEN line when MCSPI_CHCONF_0/1/2/3[6] EPOL=0, and drives it low when MCSPI_CHCONF_0/1/2/3[6] EPOL=1. 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_0/1/2/3[6] EPOL=0, and drives it high when MCSPI_CHCONF_0/1/2/3[6] EPOL=1.
19	TURBO	R/W	0h	Turbo mode 1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer. 0 Turbo is deactivated (recommended for single MCSPI word transfer).
18	IS	R/W	1h	Input Select 1 Data line 1 (SPIDAT[1]) selected for reception 0 Data line 0 (SPIDAT[0]) selected for reception
17	DPE1	R/W	1h	Transmission Enable for data line 1 [SPIDATAGZEN[1]] 1 No transmission on Data Line1 (SPIDAT[1]) 0 Data line 1 (SPIDAT[1]) selected for transmission
16	DPE0	R/W	0h	Transmission Enable for data line 0 [SPIDATAGZEN[0]] 1 No transmission on data line 0 (SPIDAT[0]) 0 Data Line0 (SPIDAT[0]) selected for transmission
15	DMAR	R/W	0h	DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 1 DMA read request enabled 0 DMA read request disabled
14	DMAW	R/W	0h	DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 1 DMA write request enabled 0 DMA write request disabled
13:12	TRM	R/W	0h	Transmit/Receive modes 3 Reserved 2 Transmit-only mode 1 Receive-only mode 0 Transmit-and-receive mode
11:7	WL	R/W	0h	SPI word length
6	EPOL	R/W	0h	SPIEN polarity 1 SPICLK is held high during the INACTIVE state 0 SPICLK is held low during the INACTIVE state
5:2	CLKD	R/W	0h	Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF[CLKG] is cleared, Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] registerThe value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0
1	POL	R/W	0h	SPICLK polarity 1 SPICLK is held high during the INACTIVE state 0 SPICLK is held low during the INACTIVE state
0	PHA	R/W	0h	SPICLK phase 1 Data are latched on even-numbered edges of SPICLK. 0 Data are latched on odd-numbered edges of SPICLK.