SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

14.2.12.1 MCSPI_CH0STAT Register (Offset = 130h) [reset = 0h]

This register provides status information about transmitter and receiver registers of channel 0

Table 5-1719 Instance Table

Figure 5-848 MCSPI_CH0STAT Name Register

Table 5-1720 MCSPI_CH0STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31:7	RESERVED_2	R	0h	Read returns 0
6	RXFFF	R	0h	Channel "i" FIFO Receive Buffer Full Status 1 FIFO receive buffer is full 0 FIFO receive buffer is not full
5	RXFFE	R	0h	Channel "i" FIFO Receive Buffer Empty Status 1 FIFO receive buffer is empty 0 FIFO receive buffer is not empty
4	TXFFF	R	0h	Channel "i" FIFO Transmit Buffer Full Status 1 FIFO transmit buffer is full 0 FIFO transmit buffer is not full
3	TXFFE	R	0h	Channel "i" FIFO Transmit Buffer Empty Status 1 FIFO transmit buffer is empty 0 FIFO transmit buffer is not empty
2	EOT	R	0h	Channel "i" End of transfer Status The definitions of beginning and end of transfer vary with master versus target and the transfer format [Transmit/Receive modes, Turbo mode] See dedicated chapters for details 1 This flag is automatically set to one at the end of an MCSPI transfer. 0 This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer).
1	TXS	R	0h	Channel "i" Transmitter Register Status 1 Register is empty. 0 Register is full.
0	RXS	R	0h	Channel "i" Receiver Register Status 1 Register is full. 0 Register is empty.