SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
This register is dedicated to enable the channel 1
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Instance Name | Physical Address |
---|---|
MCSPI0 | 5220 0148h |
MCSPI1 | 5220 1148h |
MCSPI2 | 5220 2148h |
MCSPI3 | 5220 3148h |
MCSPI4 | 5220 4148h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED_2 | |||||||
R | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED_2 | |||||||
R | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EXTCLK | |||||||
R/W | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | EN | ||||||
R | R/W | ||||||
0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:16 | RESERVED_2 | R | 0h | Read returns 0 |
15:8 | EXTCLK | R/W | 0h | Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096clock divider ratio |
7:1 | RESERVED_1 | R | 0h | Read returns 0 |
0 | EN | R/W | 0h | Channel Enable 1 Channel i is active. 0 Channel i is not active. |