SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

24.2.11.1 UART_IIR_IRDA Register (Offset = 8h) [reset = 0h]

The IIR is a read-only register, which provides the source of the interrupt in a prioritized manner.

Table 5-2291 Instance Table

Figure 5-1126 UART_IIR_IRDA Name Register

Table 5-2292 UART_IIR_IRDA Register Field Descriptions

Bit	Field	Type	Reset	Description
31:8	RESERVED	NONE	0h	Reserved
7	EOF_IT	R	0h	1 Received EOF interrupt active 0 Received EOF interrupt inactive
6	LINE_STS_IT	R	0h	1 Receiver line status interrupt active 0 Receiver line status interrupt inactive
5	TX_STATUS_IT	R	0h	1 TX status interrupt active 0 TX status interrupt inactive
4	STS_FIFO_IT	R	0h	1 Status FIFO trigger level interrupt active 0 Status FIFO trigger level interrupt inactive
3	RX_OE_IT	R	0h	1 RX overrun interrupt active 0 RX overrun interrupt inactive
2	RX_FIFO_LAST_BYTE_IT	R	0h	1 Last byte of frame in RX FIFO interrupt active 0 Last byte of frame in RX FIFO interrupt inactive
1	THR_IT	R	0h	1 THR interrupt active 0 THR interrupt inactive
0	RHR_IT	R	0h	1 RHR interrupt active 0 RHR interrupt inactive