SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
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Instance Name | Physical Address |
---|---|
UART0 | 5230 0014h |
UART1 | 5230 1014h |
UART2 | 5230 2014h |
UART3 | 5230 3014h |
UART4 | 5230 4014h |
UART5 | 5230 5014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THR_EMPTY | RESERVED | RX_STOP | RESERVED | RX_FIFO_E | |||
R | R | R | NONE | R | |||
1h | 0h | 0h | 0h | 1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:8 | RESERVED | NONE | 0h | Reserved |
7 | THR_EMPTY | R | 1h | 1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed 0 Transmit holding register (TX FIFO) is not empty |
6 | RESERVED | R | 0h | |
5 | RX_STOP | R | 0h | The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register 1 Reception is completed 0 Reception is on going or waiting for a new frame |
4:1 | RESERVED | NONE | 0h | Reserved |
0 | RX_FIFO_E | R | 1h | 1 At least one data character in the RX FIFO 0 No data in the receive FIFO |