SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.24.2.28 UART_SFLSR Register

24.2.28.1 UART_SFLSR Register (Offset = 28h) [reset = 0h]

IrDA modes only.

Reading this register effectively reads frame status information from the status FIFO (this register doesn't physically exist). Reading this register will increment the status FIFO read pointer (SFREGL and SFREGH must be read first).

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Table 5-2325 Instance Table

Instance Name	Physical Address
UART0	5230 0028h
UART1	5230 1028h
UART2	5230 2028h
UART3	5230 3028h
UART4	5230 4028h
UART5	5230 5028h

Figure 5-1143 UART_SFLSR Name Register

31	30	29	28	27	26	25	24
RESERVED_24
R
0h
23	22	21	20	19	18	17	16
RESERVED_24
R
0h
15	14	13	12	11	10	9	8
RESERVED_24
R
0h
7	6	5	4	3	2	1	0
RESERVED5			OE_ERROR	FRAME_TOO_LONG_ERROR	ABORT_DETECT	CRC_ERROR	RESERVED0
R			R	R	R	R	R
0h			0h	0h	0h	0h	0h

Table 5-2326 UART_SFLSR Register Field Descriptions

Bit	Field	Type	Reset	Description
31:8	RESERVED_24	R	0h
7:5	RESERVED5	R	0h
4	OE_ERROR	R	0h	1 Overrun error in RX FIFO when frame at top of RX FIFO was received.
3	FRAME_TOO_LONG_ERROR	R	0h	1 Frame-length too long error in frame at top of RX FIFO.
2	ABORT_DETECT	R	0h	1 Abort pattern detected in frame at top of RX FIFO
1	CRC_ERROR	R	0h	1 CRC error in frame at top of RX FIFO. top of RX FIFO = Next frame to be read from RX FIFO
0	RESERVED0	R	0h