SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
IrDA modes only.
The frame lengths of received frames are written into the status FIFO. This information can be read by reading the SFREGL and SFREGH registers (i.e. these registers do not physically exist). The least significant bits are read from SFREGL and the most significant bits are read from SFREGH. Reading these registers does not alter the status FIFO read pointer. These registers should be read before the pointer is incremented by reading the SFLSR.
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Instance Name | Physical Address |
---|---|
UART0 | 5230 0030h |
UART1 | 5230 1030h |
UART2 | 5230 2030h |
UART3 | 5230 3030h |
UART4 | 5230 4030h |
UART5 | 5230 5030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED_24 | |||||||
R | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED_24 | |||||||
R | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_24 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SFREGL | |||||||
R | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:8 | RESERVED_24 | R | 0h | |
7:0 | SFREGL | R | 0h | LSB part of the frame length |