SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.24.2.38 UART_ACREG Register

24.2.38.1 UART_ACREG Register (Offset = 3Ch) [reset = 0h]

IR-IrDA and IR-CIR modes only.

Table 5-2345 Instance Table

Instance Name	Physical Address
UART0	5230 003Ch
UART1	5230 103Ch
UART2	5230 203Ch
UART3	5230 303Ch
UART4	5230 403Ch
UART5	5230 503Ch

Figure 5-1153 UART_ACREG Name Register

31	30	29	28	27	26	25	24
RESERVED_24
R
0h
23	22	21	20	19	18	17	16
RESERVED_24
R
0h
15	14	13	12	11	10	9	8
RESERVED_24
R
0h
7	6	5	4	3	2	1	0
PULSE_TYPE	SD_MOD	DIS_IR_RX	DIS_TX_UNDERRUN	SEND_SIP	SCTX_EN	ABORT_EN	EOT_EN
R/W	R/W	R/W	R/W	R/W1TS	R/W1TS	R/W	R/W1TS
0h	0h	0h	0h	0h	0h	0h	0h

Table 5-2346 UART_ACREG Register Field Descriptions

Bit	Field	Type	Reset	Description
31:8	RESERVED_24	R	0h
7	PULSE_TYPE	R/W	0h	SIR pulse width select: 1 1.6us 0 3/16 of baud-rate pulse width
6	SD_MOD	R/W	0h	Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. 1 SD pin is set to low 0 SD pin is set to high
5	DIS_IR_RX	R/W	0h	1 Disables RX input (permanent state - independent of transmit). 0 Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation).
4	DIS_TX_UNDERRUN	R/W	0h	It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1, garbage data is sent over TX line. 1 Long stop bits can be transmitted, TX underrun is disabled 0 Long stop bits cannot be transmitted, TX underrun is enabled
3	SEND_SIP	R/W1TS	0h	MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission, the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission. 1 Send SIP pulse. 0 No action
2	SCTX_EN	R/W1TS	0h	Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing.
1	ABORT_EN	R/W	0h	Frame Abort. The LH can intentionally abort transmission of a frame by Writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1, UART IrDA will start a new transfer with data of previous frame as soon as abort frame has been sent. Therefore, TX FIFO must be reset before sending an abort frame.
0	EOT_EN	R/W1TS	0h	EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO].