SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Mode definition register 4
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Instance Name | Physical Address |
---|---|
UART0 | 5230 0088h |
UART1 | 5230 1088h |
UART2 | 5230 2088h |
UART3 | 5230 3088h |
UART4 | 5230 4088h |
UART5 | 5230 5088h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED1 | |||||||
R | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED1 | |||||||
R | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED1 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MODE9 | FREQ_SEL_H | MODE | ||||
R | R/W | R/W | R/W | ||||
0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:8 | RESERVED1 | R | 0h | |
7 | RESERVED | R | 0h | |
6 | MODE9 | R/W | 0h | 9-bit character length. When '1', overrides character length setting in LCR |
5:3 | FREQ_SEL_H | R/W | 0h | Upper 3 bits of FREQ_SEL register for higher division values, as required for example for FI/Di in ISO7816 mode |
2:0 | MODE | R/W | 0h | New modes [when set, overrides MDR1 modes] 7 reserved 6 reserved 5 ISO 7816 mode T=1 4 ISO 7816 mode T=0 3 Synchronous mode with generated clock 2 Synchronous mode with external clock 1 reserved 0 disabled (no override) |