SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Time Base Control Register.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0000h |
EPWM0_G1 | 5004 0000h |
EPWM0_G2 | 5008 0000h |
EPWM0_G3 | 500C 0000h |
EPWM1_G0 | 5000 1000h |
EPWM1_G1 | 5004 1000h |
EPWM1_G2 | 5008 1000h |
EPWM1_G3 | 500C 1000h |
EPWM2_G0 | 5000 2000h |
EPWM2_G1 | 5004 2000h |
EPWM2_G2 | 5008 2000h |
EPWM2_G3 | 500C 2000h |
EPWM3_G0 | 5000 3000h |
EPWM3_G1 | 5004 3000h |
EPWM3_G2 | 5008 3000h |
EPWM3_G3 | 500C 3000h |
EPWM4_G0 | 5000 4000h |
EPWM4_G1 | 5004 4000h |
EPWM4_G2 | 5008 4000h |
EPWM4_G3 | 500C 4000h |
EPWM5_G0 | 5000 5000h |
EPWM5_G1 | 5004 5000h |
EPWM5_G2 | 5008 5000h |
EPWM5_G3 | 500C 5000h |
EPWM6_G0 | 5000 6000h |
EPWM6_G1 | 5004 6000h |
EPWM6_G2 | 5008 6000h |
EPWM6_G3 | 500C 6000h |
EPWM7_G0 | 5000 7000h |
EPWM7_G1 | 5004 7000h |
EPWM7_G2 | 5008 7000h |
EPWM7_G3 | 500C 7000h |
EPWM8_G0 | 5000 8000h |
EPWM8_G1 | 5004 8000h |
EPWM8_G2 | 5008 8000h |
EPWM8_G3 | 500C 8000h |
EPWM9_G0 | 5000 9000h |
EPWM9_G1 | 5004 9000h |
EPWM9_G2 | 5008 9000h |
EPWM9_G3 | 500C 9000h |
EPWM10_G0 | 5000 A000h |
EPWM10_G1 | 5004 A000h |
EPWM10_G2 | 5008 A000h |
EPWM10_G3 | 500C A000h |
EPWM11_G0 | 5000 B000h |
EPWM11_G1 | 5004 B000h |
EPWM11_G2 | 5008 B000h |
EPWM11_G3 | 500C B000h |
EPWM12_G0 | 5000 C000h |
EPWM12_G1 | 5004 C000h |
EPWM12_G2 | 5008 C000h |
EPWM12_G3 | 500C C000h |
EPWM13_G0 | 5000 D000h |
EPWM13_G1 | 5004 D000h |
EPWM13_G2 | 5008 D000h |
EPWM13_G3 | 500C D000h |
EPWM14_G0 | 5000 E000h |
EPWM14_G1 | 5004 E000h |
EPWM14_G2 | 5008 E000h |
EPWM14_G3 | 500C E000h |
EPWM15_G0 | 5000 F000h |
EPWM15_G1 | 5004 F000h |
EPWM15_G2 | 5008 F000h |
EPWM15_G3 | 500C F000h |
EPWM16_G0 | 5001 0000h |
EPWM16_G1 | 5005 0000h |
EPWM16_G2 | 5009 0000h |
EPWM16_G3 | 500D 0000h |
EPWM17_G0 | 5001 1000h |
EPWM17_G1 | 5005 1000h |
EPWM17_G2 | 5009 1000h |
EPWM17_G3 | 500D 1000h |
EPWM18_G0 | 5001 2000h |
EPWM18_G1 | 5005 2000h |
EPWM18_G2 | 5009 2000h |
EPWM18_G3 | 500D 2000h |
EPWM19_G0 | 5001 3000h |
EPWM19_G1 | 5005 3000h |
EPWM19_G2 | 5009 3000h |
EPWM19_G3 | 500D 3000h |
EPWM20_G0 | 5001 4000h |
EPWM20_G1 | 5005 4000h |
EPWM20_G2 | 5009 4000h |
EPWM20_G3 | 500D 4000h |
EPWM21_G0 | 5001 5000h |
EPWM21_G1 | 5005 5000h |
EPWM21_G2 | 5009 5000h |
EPWM21_G3 | 500D 5000h |
EPWM22_G0 | 5001 6000h |
EPWM22_G1 | 5005 6000h |
EPWM22_G2 | 5009 6000h |
EPWM22_G3 | 500D 6000h |
EPWM23_G0 | 5001 7000h |
EPWM23_G1 | 5005 7000h |
EPWM23_G2 | 5009 7000h |
EPWM23_G3 | 500D 7000h |
EPWM24_G0 | 5001 8000h |
EPWM24_G1 | 5005 8000h |
EPWM24_G2 | 5009 8000h |
EPWM24_G3 | 500D 8000h |
EPWM25_G0 | 5001 9000h |
EPWM25_G1 | 5005 9000h |
EPWM25_G2 | 5009 9000h |
EPWM25_G3 | 500D 9000h |
EPWM26_G0 | 5001 A000h |
EPWM26_G1 | 5005 A000h |
EPWM26_G2 | 5009 A000h |
EPWM26_G3 | 500D A000h |
EPWM27_G0 | 5001 B000h |
EPWM27_G1 | 5005 B000h |
EPWM27_G2 | 5009 B000h |
EPWM27_G3 | 500D B000h |
EPWM28_G0 | 5001 C000h |
EPWM28_G1 | 5005 C000h |
EPWM28_G2 | 5009 C000h |
EPWM28_G3 | 500D C000h |
EPWM29_G0 | 5001 D000h |
EPWM29_G1 | 5005 D000h |
EPWM29_G2 | 5009 D000h |
EPWM29_G3 | 500D D000h |
EPWM30_G0 | 5001 E000h |
EPWM30_G1 | 5005 E000h |
EPWM30_G2 | 5009 E000h |
EPWM30_G3 | 500D E000h |
EPWM31_G0 | 5001 F000h |
EPWM31_G1 | 5005 F000h |
EPWM31_G2 | 5009 F000h |
EPWM31_G3 | 500D F000h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FREE_SOFT | PHSDIR | CLKDIV | HSPCLKDIV | ||||
R/W | R/W | R/W | R/W | ||||
0h | 0h | 0h | 1h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HSPCLKDIV | SWFSYNC | RESERVED_1 | PRDLD | PHSEN | CTRMODE | ||
R/W | R/W1TS | R | R/W | R/W | R/W | ||
1h | 0h | 0h | 0h | 0h | 3h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | FREE_SOFT | R/W | 0h | Emulation Mode Bits. These bits select the behavior of the EPWM time-base counter during emulation events 00:Stop after the next time-base counter increment or decrement 01:Stop when counter completes a whole cycle: - Up-count mode: stop when the time-base counter = period [TBCTR = TBPRD] - Down-count mode: stop when the time-base counter = 0x00 [TBCTR = 0x00] - Up-down-count mode: stop when the time-base counter = 0x00 [TBCTR = 0x00] 1x: Free run |
13 | PHSDIR | R/W | 0h | Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase value is loaded from the phase [TBPHS] register. This is irrespective of the direction of the counter before the synchronization event.. In the up-count and down-count modes this bit is ignored. 0:Count down after the synchronization event. 1:Count up after the synchronization event. |
12:10 | CLKDIV | R/W | 0h | Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000:/1 [default on reset] 001:/2 010:/4 011:/8 100:/16 101:/32 110:/64 111:/128 |
9:7 | HSPCLKDIV | R/W | 1h | High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV] peripheral. 000:/1 001:/2 [default on reset] 010:/4 011:/6 100:/8 101:/10 110:/12 111:/14 |
6 | SWFSYNC | R/W1TS | 0h | Software Forced Sync Pulse 0:Writing a 0 has no effect and reads always return a 0. 1:Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to effect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit. |
5:4 | RESERVED_1 | R | 0h | Reserved |
3 | PRDLD | R/W | 0h | Active Period Reg Load from Shadow Select 0:The period register [TBPRD] is loaded from its shadow register when the time-base counter, TBCTR, is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the TBPRD register accesses the shadow register. 1: Immediate Mode [Shadow register bypassed]: A write or read to the TBPRD register accesses the active register. |
2 | PHSEN | R/W | 0h | Counter Reg Load from Phase Reg Enable 0:Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1:Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI input signal occurs or a software-forced sync signal, see bit 6. |
1:0 | CTRMODE | R/W | 3h | Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter, the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change. These bits set the time-base counter mode of operation as follows: 00:Up-count mode 01:Down-count mode 10:Up-down count mode 11:Freeze counter operation [default on reset] |