SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Counter Compare Control Register.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0010h |
EPWM0_G1 | 5004 0010h |
EPWM0_G2 | 5008 0010h |
EPWM0_G3 | 500C 0010h |
EPWM1_G0 | 5000 1010h |
EPWM1_G1 | 5004 1010h |
EPWM1_G2 | 5008 1010h |
EPWM1_G3 | 500C 1010h |
EPWM2_G0 | 5000 2010h |
EPWM2_G1 | 5004 2010h |
EPWM2_G2 | 5008 2010h |
EPWM2_G3 | 500C 2010h |
EPWM3_G0 | 5000 3010h |
EPWM3_G1 | 5004 3010h |
EPWM3_G2 | 5008 3010h |
EPWM3_G3 | 500C 3010h |
EPWM4_G0 | 5000 4010h |
EPWM4_G1 | 5004 4010h |
EPWM4_G2 | 5008 4010h |
EPWM4_G3 | 500C 4010h |
EPWM5_G0 | 5000 5010h |
EPWM5_G1 | 5004 5010h |
EPWM5_G2 | 5008 5010h |
EPWM5_G3 | 500C 5010h |
EPWM6_G0 | 5000 6010h |
EPWM6_G1 | 5004 6010h |
EPWM6_G2 | 5008 6010h |
EPWM6_G3 | 500C 6010h |
EPWM7_G0 | 5000 7010h |
EPWM7_G1 | 5004 7010h |
EPWM7_G2 | 5008 7010h |
EPWM7_G3 | 500C 7010h |
EPWM8_G0 | 5000 8010h |
EPWM8_G1 | 5004 8010h |
EPWM8_G2 | 5008 8010h |
EPWM8_G3 | 500C 8010h |
EPWM9_G0 | 5000 9010h |
EPWM9_G1 | 5004 9010h |
EPWM9_G2 | 5008 9010h |
EPWM9_G3 | 500C 9010h |
EPWM10_G0 | 5000 A010h |
EPWM10_G1 | 5004 A010h |
EPWM10_G2 | 5008 A010h |
EPWM10_G3 | 500C A010h |
EPWM11_G0 | 5000 B010h |
EPWM11_G1 | 5004 B010h |
EPWM11_G2 | 5008 B010h |
EPWM11_G3 | 500C B010h |
EPWM12_G0 | 5000 C010h |
EPWM12_G1 | 5004 C010h |
EPWM12_G2 | 5008 C010h |
EPWM12_G3 | 500C C010h |
EPWM13_G0 | 5000 D010h |
EPWM13_G1 | 5004 D010h |
EPWM13_G2 | 5008 D010h |
EPWM13_G3 | 500C D010h |
EPWM14_G0 | 5000 E010h |
EPWM14_G1 | 5004 E010h |
EPWM14_G2 | 5008 E010h |
EPWM14_G3 | 500C E010h |
EPWM15_G0 | 5000 F010h |
EPWM15_G1 | 5004 F010h |
EPWM15_G2 | 5008 F010h |
EPWM15_G3 | 500C F010h |
EPWM16_G0 | 5001 0010h |
EPWM16_G1 | 5005 0010h |
EPWM16_G2 | 5009 0010h |
EPWM16_G3 | 500D 0010h |
EPWM17_G0 | 5001 1010h |
EPWM17_G1 | 5005 1010h |
EPWM17_G2 | 5009 1010h |
EPWM17_G3 | 500D 1010h |
EPWM18_G0 | 5001 2010h |
EPWM18_G1 | 5005 2010h |
EPWM18_G2 | 5009 2010h |
EPWM18_G3 | 500D 2010h |
EPWM19_G0 | 5001 3010h |
EPWM19_G1 | 5005 3010h |
EPWM19_G2 | 5009 3010h |
EPWM19_G3 | 500D 3010h |
EPWM20_G0 | 5001 4010h |
EPWM20_G1 | 5005 4010h |
EPWM20_G2 | 5009 4010h |
EPWM20_G3 | 500D 4010h |
EPWM21_G0 | 5001 5010h |
EPWM21_G1 | 5005 5010h |
EPWM21_G2 | 5009 5010h |
EPWM21_G3 | 500D 5010h |
EPWM22_G0 | 5001 6010h |
EPWM22_G1 | 5005 6010h |
EPWM22_G2 | 5009 6010h |
EPWM22_G3 | 500D 6010h |
EPWM23_G0 | 5001 7010h |
EPWM23_G1 | 5005 7010h |
EPWM23_G2 | 5009 7010h |
EPWM23_G3 | 500D 7010h |
EPWM24_G0 | 5001 8010h |
EPWM24_G1 | 5005 8010h |
EPWM24_G2 | 5009 8010h |
EPWM24_G3 | 500D 8010h |
EPWM25_G0 | 5001 9010h |
EPWM25_G1 | 5005 9010h |
EPWM25_G2 | 5009 9010h |
EPWM25_G3 | 500D 9010h |
EPWM26_G0 | 5001 A010h |
EPWM26_G1 | 5005 A010h |
EPWM26_G2 | 5009 A010h |
EPWM26_G3 | 500D A010h |
EPWM27_G0 | 5001 B010h |
EPWM27_G1 | 5005 B010h |
EPWM27_G2 | 5009 B010h |
EPWM27_G3 | 500D B010h |
EPWM28_G0 | 5001 C010h |
EPWM28_G1 | 5005 C010h |
EPWM28_G2 | 5009 C010h |
EPWM28_G3 | 500D C010h |
EPWM29_G0 | 5001 D010h |
EPWM29_G1 | 5005 D010h |
EPWM29_G2 | 5009 D010h |
EPWM29_G3 | 500D D010h |
EPWM30_G0 | 5001 E010h |
EPWM30_G1 | 5005 E010h |
EPWM30_G2 | 5009 E010h |
EPWM30_G3 | 500D E010h |
EPWM31_G0 | 5001 F010h |
EPWM31_G1 | 5005 F010h |
EPWM31_G2 | 5009 F010h |
EPWM31_G3 | 500D F010h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LINKDUTYHR | RESERVED_3 | LOADBSYNC | LOADASYNC | SHDWBFULL | SHDWAFULL | ||
R/W | R | R/W | R/W | R | R | ||
0h | 0h | 0h | 0h | 0h | 0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_2 | SHDWBMODE | RESERVED_1 | SHDWAMODE | LOADBMODE | LOADAMODE | ||
R | R/W | R | R/W | R/W | R/W | ||
0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | LINKDUTYHR | R/W | 0h | CMPAHR, CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR, CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary PWM output generation [Section 7 details of the operation] |
14 | RESERVED_3 | R | 0h | Reserved |
13:12 | LOADBSYNC | R/W | 0h | Shadow to Active CMPB Register Load on SYNC event 00:Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPB:CMPBHR occurs only when a SYNC is received 11:Reserved Note: This bit is valid only if CMPCTL[SHDWBMODE] = 0. |
11:10 | LOADASYNC | R/W | 0h | Shadow to Active CMPA Register Load on SYNC event 00:Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 2'b10] [same as legacy] 01:Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC occurs 10:Shadow to Active Load of CMPA:CMPAHR occurs only when a SYNC is received 11:Reserved Note: This bit is valid only if CMPCTL[SHDWAMODE] = 0. |
9 | SHDWBFULL | R | 0h | Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0:CMPB shadow FIFO not full yet 1:Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value |
8 | SHDWAFULL | R | 0h | Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not effect the flag. This bit self clears once a load-strobe occurs. 0:CMPA shadow FIFO not full yet 1:Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow value |
7 | RESERVED_2 | R | 0h | Reserved |
6 | SHDWBMODE | R/W | 0h | Counter-compare B [CMPB] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for immediate compare action |
5 | RESERVED_1 | R | 0h | Reserved |
4 | SHDWAMODE | R/W | 0h | Counter-compare A [CMPA] Register Operating Mode 0:Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1:Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for immediate compare action |
3:2 | LOADBMODE | R/W | 0h | Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD 11:Freeze [no loads possible] |
1:0 | LOADAMODE | R/W | 0h | Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD 11:Freeze [no loads possible] |