SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Dead-Band Generator Control Register.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0018h |
EPWM0_G1 | 5004 0018h |
EPWM0_G2 | 5008 0018h |
EPWM0_G3 | 500C 0018h |
EPWM1_G0 | 5000 1018h |
EPWM1_G1 | 5004 1018h |
EPWM1_G2 | 5008 1018h |
EPWM1_G3 | 500C 1018h |
EPWM2_G0 | 5000 2018h |
EPWM2_G1 | 5004 2018h |
EPWM2_G2 | 5008 2018h |
EPWM2_G3 | 500C 2018h |
EPWM3_G0 | 5000 3018h |
EPWM3_G1 | 5004 3018h |
EPWM3_G2 | 5008 3018h |
EPWM3_G3 | 500C 3018h |
EPWM4_G0 | 5000 4018h |
EPWM4_G1 | 5004 4018h |
EPWM4_G2 | 5008 4018h |
EPWM4_G3 | 500C 4018h |
EPWM5_G0 | 5000 5018h |
EPWM5_G1 | 5004 5018h |
EPWM5_G2 | 5008 5018h |
EPWM5_G3 | 500C 5018h |
EPWM6_G0 | 5000 6018h |
EPWM6_G1 | 5004 6018h |
EPWM6_G2 | 5008 6018h |
EPWM6_G3 | 500C 6018h |
EPWM7_G0 | 5000 7018h |
EPWM7_G1 | 5004 7018h |
EPWM7_G2 | 5008 7018h |
EPWM7_G3 | 500C 7018h |
EPWM8_G0 | 5000 8018h |
EPWM8_G1 | 5004 8018h |
EPWM8_G2 | 5008 8018h |
EPWM8_G3 | 500C 8018h |
EPWM9_G0 | 5000 9018h |
EPWM9_G1 | 5004 9018h |
EPWM9_G2 | 5008 9018h |
EPWM9_G3 | 500C 9018h |
EPWM10_G0 | 5000 A018h |
EPWM10_G1 | 5004 A018h |
EPWM10_G2 | 5008 A018h |
EPWM10_G3 | 500C A018h |
EPWM11_G0 | 5000 B018h |
EPWM11_G1 | 5004 B018h |
EPWM11_G2 | 5008 B018h |
EPWM11_G3 | 500C B018h |
EPWM12_G0 | 5000 C018h |
EPWM12_G1 | 5004 C018h |
EPWM12_G2 | 5008 C018h |
EPWM12_G3 | 500C C018h |
EPWM13_G0 | 5000 D018h |
EPWM13_G1 | 5004 D018h |
EPWM13_G2 | 5008 D018h |
EPWM13_G3 | 500C D018h |
EPWM14_G0 | 5000 E018h |
EPWM14_G1 | 5004 E018h |
EPWM14_G2 | 5008 E018h |
EPWM14_G3 | 500C E018h |
EPWM15_G0 | 5000 F018h |
EPWM15_G1 | 5004 F018h |
EPWM15_G2 | 5008 F018h |
EPWM15_G3 | 500C F018h |
EPWM16_G0 | 5001 0018h |
EPWM16_G1 | 5005 0018h |
EPWM16_G2 | 5009 0018h |
EPWM16_G3 | 500D 0018h |
EPWM17_G0 | 5001 1018h |
EPWM17_G1 | 5005 1018h |
EPWM17_G2 | 5009 1018h |
EPWM17_G3 | 500D 1018h |
EPWM18_G0 | 5001 2018h |
EPWM18_G1 | 5005 2018h |
EPWM18_G2 | 5009 2018h |
EPWM18_G3 | 500D 2018h |
EPWM19_G0 | 5001 3018h |
EPWM19_G1 | 5005 3018h |
EPWM19_G2 | 5009 3018h |
EPWM19_G3 | 500D 3018h |
EPWM20_G0 | 5001 4018h |
EPWM20_G1 | 5005 4018h |
EPWM20_G2 | 5009 4018h |
EPWM20_G3 | 500D 4018h |
EPWM21_G0 | 5001 5018h |
EPWM21_G1 | 5005 5018h |
EPWM21_G2 | 5009 5018h |
EPWM21_G3 | 500D 5018h |
EPWM22_G0 | 5001 6018h |
EPWM22_G1 | 5005 6018h |
EPWM22_G2 | 5009 6018h |
EPWM22_G3 | 500D 6018h |
EPWM23_G0 | 5001 7018h |
EPWM23_G1 | 5005 7018h |
EPWM23_G2 | 5009 7018h |
EPWM23_G3 | 500D 7018h |
EPWM24_G0 | 5001 8018h |
EPWM24_G1 | 5005 8018h |
EPWM24_G2 | 5009 8018h |
EPWM24_G3 | 500D 8018h |
EPWM25_G0 | 5001 9018h |
EPWM25_G1 | 5005 9018h |
EPWM25_G2 | 5009 9018h |
EPWM25_G3 | 500D 9018h |
EPWM26_G0 | 5001 A018h |
EPWM26_G1 | 5005 A018h |
EPWM26_G2 | 5009 A018h |
EPWM26_G3 | 500D A018h |
EPWM27_G0 | 5001 B018h |
EPWM27_G1 | 5005 B018h |
EPWM27_G2 | 5009 B018h |
EPWM27_G3 | 500D B018h |
EPWM28_G0 | 5001 C018h |
EPWM28_G1 | 5005 C018h |
EPWM28_G2 | 5009 C018h |
EPWM28_G3 | 500D C018h |
EPWM29_G0 | 5001 D018h |
EPWM29_G1 | 5005 D018h |
EPWM29_G2 | 5009 D018h |
EPWM29_G3 | 500D D018h |
EPWM30_G0 | 5001 E018h |
EPWM30_G1 | 5005 E018h |
EPWM30_G2 | 5009 E018h |
EPWM30_G3 | 500D E018h |
EPWM31_G0 | 5001 F018h |
EPWM31_G1 | 5005 F018h |
EPWM31_G2 | 5009 F018h |
EPWM31_G3 | 500D F018h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
HALFCYCLE | DEDB_MODE | OUTSWAP | SHDWDBFEDMODE | SHDWDBREDMODE | LOADFEDMODE | ||
R/W | R/W | R/W | R/W | R/W | R/W | ||
0h | 0h | 0h | 0h | 0h | 0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOADREDMODE | IN_MODE | POLSEL | OUT_MODE | ||||
R/W | R/W | R/W | R/W | ||||
0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | HALFCYCLE | R/W | 0h | Half Cycle Clocking Enable Bit 0:Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1:Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2. |
14 | DEDB_MODE | R/W | 0h | Dead Band Dual-Edge B Mode Control [S8 switch] 0:Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal path only. 1:Rising edge delay and falling edge delay applied to source selected by S4 switch [INMODE bits] and output to B signal path only. Note: When this bit is set to 1, user should always either set OUT_MODE bits such that Apath = InA OR OUTSWAP bits such that OutA=Bpath otherwise, OutA will be invalid. |
13:12 | OUTSWAP | R/W | 0h | Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00:OutA and OutB signals are as defined by OUT-MODE bits. 01:OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE bits [rising edge delay or delay-bypassed A signal path]. 10:OutA = B-path as defined by OUT-MODE bits [falling edge delay or delay-bypassed B signal path]. OutB = B-path as defined by OUT-MODE bits. 11:OutA = B-path as defined by OUT-MODE bits [falling edge delay or delay-bypassed B signal path]. OutB = A-path as defined by OUT-MODE bits [rising edge delay or delay-bypassed A signal path]. |
11 | SHDWDBFEDMODE | R/W | 0h | FED Dead-Band Load Mode 0:Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate "FED dead-band action." 1:Shadow mode. Operates as a double buffer. All writes via the CPU access Shadow register. Default at Reset is Immediate mode [for compatibility with legacy]. |
10 | SHDWDBREDMODE | R/W | 0h | RED Dead-Band Load Mode 0:Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate "RED dead-band action." 1:Shadow mode. Operates as a double buffer. All writes via the CPU access Shadow register. Default at Reset is Immediate mode [for compatibility with legacy]. |
9:8 | LOADFEDMODE | R/W | 0h | Active DBFED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0, or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode. |
7:6 | LOADREDMODE | R/W | 0h | Active DBRED Load from Shadow Select Mode 00:Load on Counter = 0 [CNT_eq] 01:Load on Counter = Period [PRD_eq] 10:Load on either Counter = 0, or Counter = Period 11:Freeze [no loads possible] Note: has no effect in Immediate mode. |
5:4 | IN_MODE | R/W | 0h | Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is EPWMxA In is the source for both falling and rising-edge delays. 00:EPWMxA In [from the action-qualifier] is the source for both falling-edge and rising-edge delay. 01:EPWMxB In [from the action-qualifier] is the source for rising-edge delayed signal. EPWMxA In [from the action-qualifier] is the source for falling-edge delayed signal. 10:EPWMxA In [from the action-qualifier] is the source for rising-edge delayed signal. EPWMxB In [from the action-qualifier] is the source for falling-edge delayed signal. 11:EPWMxB In [from the action-qualifier] is the source for both rising-edge delay and falling-edge delayed signal. |
3:2 | POLSEL | R/W | 0h | Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to classical upper/lower switch control as found in one leg of a digital motor control inverter. These assume that DBCTL[OUT_MODE] = 2'b11 and DBCTL[IN_MODE] = 0x0. Other enhanced modes are also possible, but not regarded as typical usage modes. 00:Active high [AH] mode. Neither EPWMxA nor EPWMxB is inverted [default]. 01:Active low complementary [ALC] mode. EPWMxA is inverted. 10:Active high complementary [AHC]. EPWMxB is inverted. 11:Active low [AL] mode. Both EPWMxA and EPWMxB are inverted. |
1:0 | OUT_MODE | R/W | 0h | Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00:DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01:Apath = InA [delay is by-passed for A signal path] Bpath = FED [Falling Edge Delay in B signal path] 10:Apath = RED [Rising Edge Delay in A signal path] Bpath = InB [delay is by-passed for B signal path] 11:DBM is fully enabled [i.e. both RED and FED active] |