SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Valley Capture Control Register.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0030h |
EPWM0_G1 | 5004 0030h |
EPWM0_G2 | 5008 0030h |
EPWM0_G3 | 500C 0030h |
EPWM1_G0 | 5000 1030h |
EPWM1_G1 | 5004 1030h |
EPWM1_G2 | 5008 1030h |
EPWM1_G3 | 500C 1030h |
EPWM2_G0 | 5000 2030h |
EPWM2_G1 | 5004 2030h |
EPWM2_G2 | 5008 2030h |
EPWM2_G3 | 500C 2030h |
EPWM3_G0 | 5000 3030h |
EPWM3_G1 | 5004 3030h |
EPWM3_G2 | 5008 3030h |
EPWM3_G3 | 500C 3030h |
EPWM4_G0 | 5000 4030h |
EPWM4_G1 | 5004 4030h |
EPWM4_G2 | 5008 4030h |
EPWM4_G3 | 500C 4030h |
EPWM5_G0 | 5000 5030h |
EPWM5_G1 | 5004 5030h |
EPWM5_G2 | 5008 5030h |
EPWM5_G3 | 500C 5030h |
EPWM6_G0 | 5000 6030h |
EPWM6_G1 | 5004 6030h |
EPWM6_G2 | 5008 6030h |
EPWM6_G3 | 500C 6030h |
EPWM7_G0 | 5000 7030h |
EPWM7_G1 | 5004 7030h |
EPWM7_G2 | 5008 7030h |
EPWM7_G3 | 500C 7030h |
EPWM8_G0 | 5000 8030h |
EPWM8_G1 | 5004 8030h |
EPWM8_G2 | 5008 8030h |
EPWM8_G3 | 500C 8030h |
EPWM9_G0 | 5000 9030h |
EPWM9_G1 | 5004 9030h |
EPWM9_G2 | 5008 9030h |
EPWM9_G3 | 500C 9030h |
EPWM10_G0 | 5000 A030h |
EPWM10_G1 | 5004 A030h |
EPWM10_G2 | 5008 A030h |
EPWM10_G3 | 500C A030h |
EPWM11_G0 | 5000 B030h |
EPWM11_G1 | 5004 B030h |
EPWM11_G2 | 5008 B030h |
EPWM11_G3 | 500C B030h |
EPWM12_G0 | 5000 C030h |
EPWM12_G1 | 5004 C030h |
EPWM12_G2 | 5008 C030h |
EPWM12_G3 | 500C C030h |
EPWM13_G0 | 5000 D030h |
EPWM13_G1 | 5004 D030h |
EPWM13_G2 | 5008 D030h |
EPWM13_G3 | 500C D030h |
EPWM14_G0 | 5000 E030h |
EPWM14_G1 | 5004 E030h |
EPWM14_G2 | 5008 E030h |
EPWM14_G3 | 500C E030h |
EPWM15_G0 | 5000 F030h |
EPWM15_G1 | 5004 F030h |
EPWM15_G2 | 5008 F030h |
EPWM15_G3 | 500C F030h |
EPWM16_G0 | 5001 0030h |
EPWM16_G1 | 5005 0030h |
EPWM16_G2 | 5009 0030h |
EPWM16_G3 | 500D 0030h |
EPWM17_G0 | 5001 1030h |
EPWM17_G1 | 5005 1030h |
EPWM17_G2 | 5009 1030h |
EPWM17_G3 | 500D 1030h |
EPWM18_G0 | 5001 2030h |
EPWM18_G1 | 5005 2030h |
EPWM18_G2 | 5009 2030h |
EPWM18_G3 | 500D 2030h |
EPWM19_G0 | 5001 3030h |
EPWM19_G1 | 5005 3030h |
EPWM19_G2 | 5009 3030h |
EPWM19_G3 | 500D 3030h |
EPWM20_G0 | 5001 4030h |
EPWM20_G1 | 5005 4030h |
EPWM20_G2 | 5009 4030h |
EPWM20_G3 | 500D 4030h |
EPWM21_G0 | 5001 5030h |
EPWM21_G1 | 5005 5030h |
EPWM21_G2 | 5009 5030h |
EPWM21_G3 | 500D 5030h |
EPWM22_G0 | 5001 6030h |
EPWM22_G1 | 5005 6030h |
EPWM22_G2 | 5009 6030h |
EPWM22_G3 | 500D 6030h |
EPWM23_G0 | 5001 7030h |
EPWM23_G1 | 5005 7030h |
EPWM23_G2 | 5009 7030h |
EPWM23_G3 | 500D 7030h |
EPWM24_G0 | 5001 8030h |
EPWM24_G1 | 5005 8030h |
EPWM24_G2 | 5009 8030h |
EPWM24_G3 | 500D 8030h |
EPWM25_G0 | 5001 9030h |
EPWM25_G1 | 5005 9030h |
EPWM25_G2 | 5009 9030h |
EPWM25_G3 | 500D 9030h |
EPWM26_G0 | 5001 A030h |
EPWM26_G1 | 5005 A030h |
EPWM26_G2 | 5009 A030h |
EPWM26_G3 | 500D A030h |
EPWM27_G0 | 5001 B030h |
EPWM27_G1 | 5005 B030h |
EPWM27_G2 | 5009 B030h |
EPWM27_G3 | 500D B030h |
EPWM28_G0 | 5001 C030h |
EPWM28_G1 | 5005 C030h |
EPWM28_G2 | 5009 C030h |
EPWM28_G3 | 500D C030h |
EPWM29_G0 | 5001 D030h |
EPWM29_G1 | 5005 D030h |
EPWM29_G2 | 5009 D030h |
EPWM29_G3 | 500D D030h |
EPWM30_G0 | 5001 E030h |
EPWM30_G1 | 5005 E030h |
EPWM30_G2 | 5009 E030h |
EPWM30_G3 | 500D E030h |
EPWM31_G0 | 5001 F030h |
EPWM31_G1 | 5005 F030h |
EPWM31_G2 | 5009 F030h |
EPWM31_G3 | 500D F030h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_2 | EDGEFILTDLYSEL | VDELAYDIV | |||||
R | R/W | R/W | |||||
0h | 0h | 0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDELAYDIV | RESERVED_1 | TRIGSEL | VCAPSTART | VCAPE | |||
R/W | R | R/W | R/W1TS | R/W | |||
0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:11 | RESERVED_2 | R | 0h | Reserved |
10 | EDGEFILTDLYSEL | R/W | 0h | Valley Switching Mode Delay Selection 0:No delay applied to the edge filter output 1:HWDELAYVAL delay applied to the edge filter output |
9:7 | VDELAYDIV | R/W | 0h | Valley Delay Mode Divide Enable 000:HWVDELVAL = SWVDELVAL 001:HWVDELVAL = VCNTVAL+SWVDELVAL 010:HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011:HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100:HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the consecutive edge captures can optionally be divided by using these bits. |
6:5 | RESERVED_1 | R | 0h | Reserved |
4:2 | TRIGSEL | R/W | 0h | Status of Numbered of Captured Events 000:Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001:Capture sequence is triggered by CNT_zero event. 010:Capture sequence is triggered by PRD_eq event. 011:Capture sequence is triggered by CNT_zero or PRD_eq event. 100:Capture sequence is triggered by DCAEVT1 event. 101:Capture sequence is triggered by DCAEVT2 event. 110:Capture sequence is triggered by DCBEVT1 event. 111:Capture sequence is triggered by DCBEVT2 event. Note: Valley capture sequence triggered by the selected event in this register field. Once the chosen event occurs the capture sequence is armed. Event captures occur based of the event chosen in DCFCTL[SRCSEL] register. Note: Same event may not be chosen in both DCFCTL[SRCSEL] and VCAPCTL[TRIGSEL] registers. Note: Once the chosen event in VCAPCTL[TRIGSEL] occurs, irrespective of the current capture status, capture sequence is retriggered. |
1 | VCAPSTART | R/W1TS | 0h | Valley Capture Start 0:Writing a 0 has no effect 1:Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for this bit to have any effect. Writing of 1 will result in one capture sequence trigger. |
0 | VCAPE | R/W | 0h | Valley Capture Enable/Disable 0:Disabled 1:Enabled |