SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
HRPWM Configuration Register
This register is only accessible on EPWM modules with HRPWM capabilities.
Return to Summary Table
Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0040h |
EPWM0_G1 | 5004 0040h |
EPWM0_G2 | 5008 0040h |
EPWM0_G3 | 500C 0040h |
EPWM1_G0 | 5000 1040h |
EPWM1_G1 | 5004 1040h |
EPWM1_G2 | 5008 1040h |
EPWM1_G3 | 500C 1040h |
EPWM2_G0 | 5000 2040h |
EPWM2_G1 | 5004 2040h |
EPWM2_G2 | 5008 2040h |
EPWM2_G3 | 500C 2040h |
EPWM3_G0 | 5000 3040h |
EPWM3_G1 | 5004 3040h |
EPWM3_G2 | 5008 3040h |
EPWM3_G3 | 500C 3040h |
EPWM4_G0 | 5000 4040h |
EPWM4_G1 | 5004 4040h |
EPWM4_G2 | 5008 4040h |
EPWM4_G3 | 500C 4040h |
EPWM5_G0 | 5000 5040h |
EPWM5_G1 | 5004 5040h |
EPWM5_G2 | 5008 5040h |
EPWM5_G3 | 500C 5040h |
EPWM6_G0 | 5000 6040h |
EPWM6_G1 | 5004 6040h |
EPWM6_G2 | 5008 6040h |
EPWM6_G3 | 500C 6040h |
EPWM7_G0 | 5000 7040h |
EPWM7_G1 | 5004 7040h |
EPWM7_G2 | 5008 7040h |
EPWM7_G3 | 500C 7040h |
EPWM8_G0 | 5000 8040h |
EPWM8_G1 | 5004 8040h |
EPWM8_G2 | 5008 8040h |
EPWM8_G3 | 500C 8040h |
EPWM9_G0 | 5000 9040h |
EPWM9_G1 | 5004 9040h |
EPWM9_G2 | 5008 9040h |
EPWM9_G3 | 500C 9040h |
EPWM10_G0 | 5000 A040h |
EPWM10_G1 | 5004 A040h |
EPWM10_G2 | 5008 A040h |
EPWM10_G3 | 500C A040h |
EPWM11_G0 | 5000 B040h |
EPWM11_G1 | 5004 B040h |
EPWM11_G2 | 5008 B040h |
EPWM11_G3 | 500C B040h |
EPWM12_G0 | 5000 C040h |
EPWM12_G1 | 5004 C040h |
EPWM12_G2 | 5008 C040h |
EPWM12_G3 | 500C C040h |
EPWM13_G0 | 5000 D040h |
EPWM13_G1 | 5004 D040h |
EPWM13_G2 | 5008 D040h |
EPWM13_G3 | 500C D040h |
EPWM14_G0 | 5000 E040h |
EPWM14_G1 | 5004 E040h |
EPWM14_G2 | 5008 E040h |
EPWM14_G3 | 500C E040h |
EPWM15_G0 | 5000 F040h |
EPWM15_G1 | 5004 F040h |
EPWM15_G2 | 5008 F040h |
EPWM15_G3 | 500C F040h |
EPWM16_G0 | 5001 0040h |
EPWM16_G1 | 5005 0040h |
EPWM16_G2 | 5009 0040h |
EPWM16_G3 | 500D 0040h |
EPWM17_G0 | 5001 1040h |
EPWM17_G1 | 5005 1040h |
EPWM17_G2 | 5009 1040h |
EPWM17_G3 | 500D 1040h |
EPWM18_G0 | 5001 2040h |
EPWM18_G1 | 5005 2040h |
EPWM18_G2 | 5009 2040h |
EPWM18_G3 | 500D 2040h |
EPWM19_G0 | 5001 3040h |
EPWM19_G1 | 5005 3040h |
EPWM19_G2 | 5009 3040h |
EPWM19_G3 | 500D 3040h |
EPWM20_G0 | 5001 4040h |
EPWM20_G1 | 5005 4040h |
EPWM20_G2 | 5009 4040h |
EPWM20_G3 | 500D 4040h |
EPWM21_G0 | 5001 5040h |
EPWM21_G1 | 5005 5040h |
EPWM21_G2 | 5009 5040h |
EPWM21_G3 | 500D 5040h |
EPWM22_G0 | 5001 6040h |
EPWM22_G1 | 5005 6040h |
EPWM22_G2 | 5009 6040h |
EPWM22_G3 | 500D 6040h |
EPWM23_G0 | 5001 7040h |
EPWM23_G1 | 5005 7040h |
EPWM23_G2 | 5009 7040h |
EPWM23_G3 | 500D 7040h |
EPWM24_G0 | 5001 8040h |
EPWM24_G1 | 5005 8040h |
EPWM24_G2 | 5009 8040h |
EPWM24_G3 | 500D 8040h |
EPWM25_G0 | 5001 9040h |
EPWM25_G1 | 5005 9040h |
EPWM25_G2 | 5009 9040h |
EPWM25_G3 | 500D 9040h |
EPWM26_G0 | 5001 A040h |
EPWM26_G1 | 5005 A040h |
EPWM26_G2 | 5009 A040h |
EPWM26_G3 | 500D A040h |
EPWM27_G0 | 5001 B040h |
EPWM27_G1 | 5005 B040h |
EPWM27_G2 | 5009 B040h |
EPWM27_G3 | 500D B040h |
EPWM28_G0 | 5001 C040h |
EPWM28_G1 | 5005 C040h |
EPWM28_G2 | 5009 C040h |
EPWM28_G3 | 500D C040h |
EPWM29_G0 | 5001 D040h |
EPWM29_G1 | 5005 D040h |
EPWM29_G2 | 5009 D040h |
EPWM29_G3 | 500D D040h |
EPWM30_G0 | 5001 E040h |
EPWM30_G1 | 5005 E040h |
EPWM30_G2 | 5009 E040h |
EPWM30_G3 | 500D E040h |
EPWM31_G0 | 5001 F040h |
EPWM31_G1 | 5005 F040h |
EPWM31_G2 | 5009 F040h |
EPWM31_G3 | 500D F040h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LINESEL | RESERVED_1 | HRLOADB | CTLMODEB | EDGMODEB | |||
R/W | R | R/W | R/W | R/W | |||
0h | 0h | 0h | 0h | 0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWAPAB | AUTOCONV | SELOUTB | HRLOAD | CTLMODE | EDGMODE | ||
R/W | R/W | R/W | R/W | R/W | R/W | ||
0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | LINESEL | R/W | 0h | Delay Line Selection Bits: Selects which of the 4 delay lines for a particular EPWM/EPWM module to send to CALIN for calibration. |
13 | RESERVED_1 | R | 0h | Reserved |
12:11 | HRLOADB | R/W | 0h | Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD 11:Load on CMPB_EQ [Translator Event CMPB-3] |
10 | CTLMODEB | R/W | 0h | Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e., this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the edge position [i.e., this is phase control mode]. |
9:8 | EDGMODEB | R/W | 0h | Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPBHR] 10:MEP control of falling edge [CMPBHR] 11:MEP control of both edges [TBPHSHR or TBPRDHR] |
7 | SWAPAB | R/W | 0h | Swap EPWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0:EPWMxA and EPWMxB outputs are unchanged. 1:EPWMxA signal appears on EPWMxB output and EPWMxB signal appears on EPWMxA output. |
6 | AUTOCONV | R/W | 0h | Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in application software. The SFO library function automatically updates the HRMSTEP register with the appropriate MEP scale factor. 0:Automatic HRMSTEP scaling is disabled. 1:Automatic HRMSTEP scaling is enabled. If application software is manually scaling the fractional duty cycle, or phase [i.e. software sets CMPAHR = [fraction[PWMduty * PWMperiod] * MEP Scale Factor]<<8 + 0x080 for duty cycle], then this mode must be disabled. |
5 | SELOUTB | R/W | 0h | EPWMxB Output Select Bit This bit selects which signal is output on the EPWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion takes place as the last step in modifying the EPWMxB signal. 0:EPWMxB output is normal. 1:EPWMxB output is inverted version of EPWMxA signal. |
4:3 | HRLOAD | R/W | 0h | Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00:Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01:Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10:Load on either CTR = Zero or CTR = PRD 11:Load on CMPA_EQ [Translator Event CMPA-3] |
2 | CTLMODE | R/W | 0h | Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0:CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e., this is duty or period control mode]. [Default on Reset] 1:TBPHSHR[8] Register controls the edge position [i.e., this is phase control mode]. |
1:0 | EDGMODE | R/W | 0h | Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00:HRPWM capability is disabled [default on reset] 01:MEP control of rising edge [CMPAHR] 10:MEP control of falling edge [CMPAHR] 11:MEP control of both edges [TBPHSHR or TBPRDHR] |