SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
HRPWM High Resolution Remainder Register
This register is only accessible on EPWM modules with HRPWM capabilities.
Return to Summary Table
Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 005Ch |
EPWM0_G1 | 5004 005Ch |
EPWM0_G2 | 5008 005Ch |
EPWM0_G3 | 500C 005Ch |
EPWM1_G0 | 5000 105Ch |
EPWM1_G1 | 5004 105Ch |
EPWM1_G2 | 5008 105Ch |
EPWM1_G3 | 500C 105Ch |
EPWM2_G0 | 5000 205Ch |
EPWM2_G1 | 5004 205Ch |
EPWM2_G2 | 5008 205Ch |
EPWM2_G3 | 500C 205Ch |
EPWM3_G0 | 5000 305Ch |
EPWM3_G1 | 5004 305Ch |
EPWM3_G2 | 5008 305Ch |
EPWM3_G3 | 500C 305Ch |
EPWM4_G0 | 5000 405Ch |
EPWM4_G1 | 5004 405Ch |
EPWM4_G2 | 5008 405Ch |
EPWM4_G3 | 500C 405Ch |
EPWM5_G0 | 5000 505Ch |
EPWM5_G1 | 5004 505Ch |
EPWM5_G2 | 5008 505Ch |
EPWM5_G3 | 500C 505Ch |
EPWM6_G0 | 5000 605Ch |
EPWM6_G1 | 5004 605Ch |
EPWM6_G2 | 5008 605Ch |
EPWM6_G3 | 500C 605Ch |
EPWM7_G0 | 5000 705Ch |
EPWM7_G1 | 5004 705Ch |
EPWM7_G2 | 5008 705Ch |
EPWM7_G3 | 500C 705Ch |
EPWM8_G0 | 5000 805Ch |
EPWM8_G1 | 5004 805Ch |
EPWM8_G2 | 5008 805Ch |
EPWM8_G3 | 500C 805Ch |
EPWM9_G0 | 5000 905Ch |
EPWM9_G1 | 5004 905Ch |
EPWM9_G2 | 5008 905Ch |
EPWM9_G3 | 500C 905Ch |
EPWM10_G0 | 5000 A05Ch |
EPWM10_G1 | 5004 A05Ch |
EPWM10_G2 | 5008 A05Ch |
EPWM10_G3 | 500C A05Ch |
EPWM11_G0 | 5000 B05Ch |
EPWM11_G1 | 5004 B05Ch |
EPWM11_G2 | 5008 B05Ch |
EPWM11_G3 | 500C B05Ch |
EPWM12_G0 | 5000 C05Ch |
EPWM12_G1 | 5004 C05Ch |
EPWM12_G2 | 5008 C05Ch |
EPWM12_G3 | 500C C05Ch |
EPWM13_G0 | 5000 D05Ch |
EPWM13_G1 | 5004 D05Ch |
EPWM13_G2 | 5008 D05Ch |
EPWM13_G3 | 500C D05Ch |
EPWM14_G0 | 5000 E05Ch |
EPWM14_G1 | 5004 E05Ch |
EPWM14_G2 | 5008 E05Ch |
EPWM14_G3 | 500C E05Ch |
EPWM15_G0 | 5000 F05Ch |
EPWM15_G1 | 5004 F05Ch |
EPWM15_G2 | 5008 F05Ch |
EPWM15_G3 | 500C F05Ch |
EPWM16_G0 | 5001 005Ch |
EPWM16_G1 | 5005 005Ch |
EPWM16_G2 | 5009 005Ch |
EPWM16_G3 | 500D 005Ch |
EPWM17_G0 | 5001 105Ch |
EPWM17_G1 | 5005 105Ch |
EPWM17_G2 | 5009 105Ch |
EPWM17_G3 | 500D 105Ch |
EPWM18_G0 | 5001 205Ch |
EPWM18_G1 | 5005 205Ch |
EPWM18_G2 | 5009 205Ch |
EPWM18_G3 | 500D 205Ch |
EPWM19_G0 | 5001 305Ch |
EPWM19_G1 | 5005 305Ch |
EPWM19_G2 | 5009 305Ch |
EPWM19_G3 | 500D 305Ch |
EPWM20_G0 | 5001 405Ch |
EPWM20_G1 | 5005 405Ch |
EPWM20_G2 | 5009 405Ch |
EPWM20_G3 | 500D 405Ch |
EPWM21_G0 | 5001 505Ch |
EPWM21_G1 | 5005 505Ch |
EPWM21_G2 | 5009 505Ch |
EPWM21_G3 | 500D 505Ch |
EPWM22_G0 | 5001 605Ch |
EPWM22_G1 | 5005 605Ch |
EPWM22_G2 | 5009 605Ch |
EPWM22_G3 | 500D 605Ch |
EPWM23_G0 | 5001 705Ch |
EPWM23_G1 | 5005 705Ch |
EPWM23_G2 | 5009 705Ch |
EPWM23_G3 | 500D 705Ch |
EPWM24_G0 | 5001 805Ch |
EPWM24_G1 | 5005 805Ch |
EPWM24_G2 | 5009 805Ch |
EPWM24_G3 | 500D 805Ch |
EPWM25_G0 | 5001 905Ch |
EPWM25_G1 | 5005 905Ch |
EPWM25_G2 | 5009 905Ch |
EPWM25_G3 | 500D 905Ch |
EPWM26_G0 | 5001 A05Ch |
EPWM26_G1 | 5005 A05Ch |
EPWM26_G2 | 5009 A05Ch |
EPWM26_G3 | 500D A05Ch |
EPWM27_G0 | 5001 B05Ch |
EPWM27_G1 | 5005 B05Ch |
EPWM27_G2 | 5009 B05Ch |
EPWM27_G3 | 500D B05Ch |
EPWM28_G0 | 5001 C05Ch |
EPWM28_G1 | 5005 C05Ch |
EPWM28_G2 | 5009 C05Ch |
EPWM28_G3 | 500D C05Ch |
EPWM29_G0 | 5001 D05Ch |
EPWM29_G1 | 5005 D05Ch |
EPWM29_G2 | 5009 D05Ch |
EPWM29_G3 | 500D D05Ch |
EPWM30_G0 | 5001 E05Ch |
EPWM30_G1 | 5005 E05Ch |
EPWM30_G2 | 5009 E05Ch |
EPWM30_G3 | 500D E05Ch |
EPWM31_G0 | 5001 F05Ch |
EPWM31_G1 | 5005 F05Ch |
EPWM31_G2 | 5009 F05Ch |
EPWM31_G3 | 500D F05Ch |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_1 | TRREM | ||||||
R | R/W | ||||||
0h | 0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRREM | |||||||
R/W | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:11 | RESERVED_1 | R | 0h | Reserved |
10:0 | TRREM | R/W | 0h | HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register can be automatically initialized with the TBPHSHR value on a SYNCIN or TBCTL[SWFSYNC] event or DC event [if enabled]. The user can also write a value with the CPU. 2. Priority of TRREM register updates: Sync [software or hardware] TBPHSHR copied to TRREM : Highest Priority HRPWM Hardware [updates TRREM register]: Next priority CPU Write To TRREM Register: Lowest Priority 3. Bit 10 of TRREM register is not used in asymmetrical mode. This bit can be forced to zero. TRREM will be initialized to 0x0 and 0x100 in Up and Up-down modes respectively. Asymmetrical Mode: TRREM[7:0] = TBPHSHR[15:8] TRREM[10,9,8] = 3'b000 Symmetrical Mode: TRREM[7:0] = TBPHSHR[15:8] TRREM[10,9,8] = 3'b001 |