SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Time Base Phase High.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 00C0h |
EPWM0_G1 | 5004 00C0h |
EPWM0_G2 | 5008 00C0h |
EPWM0_G3 | 500C 00C0h |
EPWM1_G0 | 5000 10C0h |
EPWM1_G1 | 5004 10C0h |
EPWM1_G2 | 5008 10C0h |
EPWM1_G3 | 500C 10C0h |
EPWM2_G0 | 5000 20C0h |
EPWM2_G1 | 5004 20C0h |
EPWM2_G2 | 5008 20C0h |
EPWM2_G3 | 500C 20C0h |
EPWM3_G0 | 5000 30C0h |
EPWM3_G1 | 5004 30C0h |
EPWM3_G2 | 5008 30C0h |
EPWM3_G3 | 500C 30C0h |
EPWM4_G0 | 5000 40C0h |
EPWM4_G1 | 5004 40C0h |
EPWM4_G2 | 5008 40C0h |
EPWM4_G3 | 500C 40C0h |
EPWM5_G0 | 5000 50C0h |
EPWM5_G1 | 5004 50C0h |
EPWM5_G2 | 5008 50C0h |
EPWM5_G3 | 500C 50C0h |
EPWM6_G0 | 5000 60C0h |
EPWM6_G1 | 5004 60C0h |
EPWM6_G2 | 5008 60C0h |
EPWM6_G3 | 500C 60C0h |
EPWM7_G0 | 5000 70C0h |
EPWM7_G1 | 5004 70C0h |
EPWM7_G2 | 5008 70C0h |
EPWM7_G3 | 500C 70C0h |
EPWM8_G0 | 5000 80C0h |
EPWM8_G1 | 5004 80C0h |
EPWM8_G2 | 5008 80C0h |
EPWM8_G3 | 500C 80C0h |
EPWM9_G0 | 5000 90C0h |
EPWM9_G1 | 5004 90C0h |
EPWM9_G2 | 5008 90C0h |
EPWM9_G3 | 500C 90C0h |
EPWM10_G0 | 5000 A0C0h |
EPWM10_G1 | 5004 A0C0h |
EPWM10_G2 | 5008 A0C0h |
EPWM10_G3 | 500C A0C0h |
EPWM11_G0 | 5000 B0C0h |
EPWM11_G1 | 5004 B0C0h |
EPWM11_G2 | 5008 B0C0h |
EPWM11_G3 | 500C B0C0h |
EPWM12_G0 | 5000 C0C0h |
EPWM12_G1 | 5004 C0C0h |
EPWM12_G2 | 5008 C0C0h |
EPWM12_G3 | 500C C0C0h |
EPWM13_G0 | 5000 D0C0h |
EPWM13_G1 | 5004 D0C0h |
EPWM13_G2 | 5008 D0C0h |
EPWM13_G3 | 500C D0C0h |
EPWM14_G0 | 5000 E0C0h |
EPWM14_G1 | 5004 E0C0h |
EPWM14_G2 | 5008 E0C0h |
EPWM14_G3 | 500C E0C0h |
EPWM15_G0 | 5000 F0C0h |
EPWM15_G1 | 5004 F0C0h |
EPWM15_G2 | 5008 F0C0h |
EPWM15_G3 | 500C F0C0h |
EPWM16_G0 | 5001 00C0h |
EPWM16_G1 | 5005 00C0h |
EPWM16_G2 | 5009 00C0h |
EPWM16_G3 | 500D 00C0h |
EPWM17_G0 | 5001 10C0h |
EPWM17_G1 | 5005 10C0h |
EPWM17_G2 | 5009 10C0h |
EPWM17_G3 | 500D 10C0h |
EPWM18_G0 | 5001 20C0h |
EPWM18_G1 | 5005 20C0h |
EPWM18_G2 | 5009 20C0h |
EPWM18_G3 | 500D 20C0h |
EPWM19_G0 | 5001 30C0h |
EPWM19_G1 | 5005 30C0h |
EPWM19_G2 | 5009 30C0h |
EPWM19_G3 | 500D 30C0h |
EPWM20_G0 | 5001 40C0h |
EPWM20_G1 | 5005 40C0h |
EPWM20_G2 | 5009 40C0h |
EPWM20_G3 | 500D 40C0h |
EPWM21_G0 | 5001 50C0h |
EPWM21_G1 | 5005 50C0h |
EPWM21_G2 | 5009 50C0h |
EPWM21_G3 | 500D 50C0h |
EPWM22_G0 | 5001 60C0h |
EPWM22_G1 | 5005 60C0h |
EPWM22_G2 | 5009 60C0h |
EPWM22_G3 | 500D 60C0h |
EPWM23_G0 | 5001 70C0h |
EPWM23_G1 | 5005 70C0h |
EPWM23_G2 | 5009 70C0h |
EPWM23_G3 | 500D 70C0h |
EPWM24_G0 | 5001 80C0h |
EPWM24_G1 | 5005 80C0h |
EPWM24_G2 | 5009 80C0h |
EPWM24_G3 | 500D 80C0h |
EPWM25_G0 | 5001 90C0h |
EPWM25_G1 | 5005 90C0h |
EPWM25_G2 | 5009 90C0h |
EPWM25_G3 | 500D 90C0h |
EPWM26_G0 | 5001 A0C0h |
EPWM26_G1 | 5005 A0C0h |
EPWM26_G2 | 5009 A0C0h |
EPWM26_G3 | 500D A0C0h |
EPWM27_G0 | 5001 B0C0h |
EPWM27_G1 | 5005 B0C0h |
EPWM27_G2 | 5009 B0C0h |
EPWM27_G3 | 500D B0C0h |
EPWM28_G0 | 5001 C0C0h |
EPWM28_G1 | 5005 C0C0h |
EPWM28_G2 | 5009 C0C0h |
EPWM28_G3 | 500D C0C0h |
EPWM29_G0 | 5001 D0C0h |
EPWM29_G1 | 5005 D0C0h |
EPWM29_G2 | 5009 D0C0h |
EPWM29_G3 | 500D D0C0h |
EPWM30_G0 | 5001 E0C0h |
EPWM30_G1 | 5005 E0C0h |
EPWM30_G2 | 5009 E0C0h |
EPWM30_G3 | 500D E0C0h |
EPWM31_G0 | 5001 F0C0h |
EPWM31_G1 | 5005 F0C0h |
EPWM31_G2 | 5009 F0C0h |
EPWM31_G3 | 500D F0C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TBPHS | |||||||
R/W | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TBPHS | |||||||
R/W | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TBPHSHR | |||||||
R/W | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBPHSHR | |||||||
R/W | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:16 | TBPHS | R/W | 0h | Phase Offset Register These bits set time-base counter phase of the selected EPWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0, then the synchronization event is ignored and the time-base counter is not loaded with the phase. - If TBCTL[PHSEN] = 1, then the time-base counter [TBCTR] will be loaded with the phase [TBPHS] when a synchronization event occurs. The synchronization event can be initiated by the input synchronization signal [EPWMxSYNCI] or by a software forced synchronization. |
15:0 | TBPHSHR | R/W | 0h | Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return zero |