SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Trip Zone Flag Register.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0126h |
EPWM0_G1 | 5004 0126h |
EPWM0_G2 | 5008 0126h |
EPWM0_G3 | 500C 0126h |
EPWM1_G0 | 5000 1126h |
EPWM1_G1 | 5004 1126h |
EPWM1_G2 | 5008 1126h |
EPWM1_G3 | 500C 1126h |
EPWM2_G0 | 5000 2126h |
EPWM2_G1 | 5004 2126h |
EPWM2_G2 | 5008 2126h |
EPWM2_G3 | 500C 2126h |
EPWM3_G0 | 5000 3126h |
EPWM3_G1 | 5004 3126h |
EPWM3_G2 | 5008 3126h |
EPWM3_G3 | 500C 3126h |
EPWM4_G0 | 5000 4126h |
EPWM4_G1 | 5004 4126h |
EPWM4_G2 | 5008 4126h |
EPWM4_G3 | 500C 4126h |
EPWM5_G0 | 5000 5126h |
EPWM5_G1 | 5004 5126h |
EPWM5_G2 | 5008 5126h |
EPWM5_G3 | 500C 5126h |
EPWM6_G0 | 5000 6126h |
EPWM6_G1 | 5004 6126h |
EPWM6_G2 | 5008 6126h |
EPWM6_G3 | 500C 6126h |
EPWM7_G0 | 5000 7126h |
EPWM7_G1 | 5004 7126h |
EPWM7_G2 | 5008 7126h |
EPWM7_G3 | 500C 7126h |
EPWM8_G0 | 5000 8126h |
EPWM8_G1 | 5004 8126h |
EPWM8_G2 | 5008 8126h |
EPWM8_G3 | 500C 8126h |
EPWM9_G0 | 5000 9126h |
EPWM9_G1 | 5004 9126h |
EPWM9_G2 | 5008 9126h |
EPWM9_G3 | 500C 9126h |
EPWM10_G0 | 5000 A126h |
EPWM10_G1 | 5004 A126h |
EPWM10_G2 | 5008 A126h |
EPWM10_G3 | 500C A126h |
EPWM11_G0 | 5000 B126h |
EPWM11_G1 | 5004 B126h |
EPWM11_G2 | 5008 B126h |
EPWM11_G3 | 500C B126h |
EPWM12_G0 | 5000 C126h |
EPWM12_G1 | 5004 C126h |
EPWM12_G2 | 5008 C126h |
EPWM12_G3 | 500C C126h |
EPWM13_G0 | 5000 D126h |
EPWM13_G1 | 5004 D126h |
EPWM13_G2 | 5008 D126h |
EPWM13_G3 | 500C D126h |
EPWM14_G0 | 5000 E126h |
EPWM14_G1 | 5004 E126h |
EPWM14_G2 | 5008 E126h |
EPWM14_G3 | 500C E126h |
EPWM15_G0 | 5000 F126h |
EPWM15_G1 | 5004 F126h |
EPWM15_G2 | 5008 F126h |
EPWM15_G3 | 500C F126h |
EPWM16_G0 | 5001 0126h |
EPWM16_G1 | 5005 0126h |
EPWM16_G2 | 5009 0126h |
EPWM16_G3 | 500D 0126h |
EPWM17_G0 | 5001 1126h |
EPWM17_G1 | 5005 1126h |
EPWM17_G2 | 5009 1126h |
EPWM17_G3 | 500D 1126h |
EPWM18_G0 | 5001 2126h |
EPWM18_G1 | 5005 2126h |
EPWM18_G2 | 5009 2126h |
EPWM18_G3 | 500D 2126h |
EPWM19_G0 | 5001 3126h |
EPWM19_G1 | 5005 3126h |
EPWM19_G2 | 5009 3126h |
EPWM19_G3 | 500D 3126h |
EPWM20_G0 | 5001 4126h |
EPWM20_G1 | 5005 4126h |
EPWM20_G2 | 5009 4126h |
EPWM20_G3 | 500D 4126h |
EPWM21_G0 | 5001 5126h |
EPWM21_G1 | 5005 5126h |
EPWM21_G2 | 5009 5126h |
EPWM21_G3 | 500D 5126h |
EPWM22_G0 | 5001 6126h |
EPWM22_G1 | 5005 6126h |
EPWM22_G2 | 5009 6126h |
EPWM22_G3 | 500D 6126h |
EPWM23_G0 | 5001 7126h |
EPWM23_G1 | 5005 7126h |
EPWM23_G2 | 5009 7126h |
EPWM23_G3 | 500D 7126h |
EPWM24_G0 | 5001 8126h |
EPWM24_G1 | 5005 8126h |
EPWM24_G2 | 5009 8126h |
EPWM24_G3 | 500D 8126h |
EPWM25_G0 | 5001 9126h |
EPWM25_G1 | 5005 9126h |
EPWM25_G2 | 5009 9126h |
EPWM25_G3 | 500D 9126h |
EPWM26_G0 | 5001 A126h |
EPWM26_G1 | 5005 A126h |
EPWM26_G2 | 5009 A126h |
EPWM26_G3 | 500D A126h |
EPWM27_G0 | 5001 B126h |
EPWM27_G1 | 5005 B126h |
EPWM27_G2 | 5009 B126h |
EPWM27_G3 | 500D B126h |
EPWM28_G0 | 5001 C126h |
EPWM28_G1 | 5005 C126h |
EPWM28_G2 | 5009 C126h |
EPWM28_G3 | 500D C126h |
EPWM29_G0 | 5001 D126h |
EPWM29_G1 | 5005 D126h |
EPWM29_G2 | 5009 D126h |
EPWM29_G3 | 500D D126h |
EPWM30_G0 | 5001 E126h |
EPWM30_G1 | 5005 E126h |
EPWM30_G2 | 5009 E126h |
EPWM30_G3 | 500D E126h |
EPWM31_G0 | 5001 F126h |
EPWM31_G1 | 5005 F126h |
EPWM31_G2 | 5009 F126h |
EPWM31_G3 | 500D F126h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_1 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPEVT | DCBEVT2 | DCBEVT1 | DCAEVT2 | DCAEVT1 | OST | CBC | INT |
R | R | R | R | R | R | R | R |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | RESERVED_1 | R | 0h | Reserved |
7 | CAPEVT | R | 0h | Latched Status Flag for Capture Event 0:Indicates no trip event has occurred on CAPEVT 1:Indicates a trip event has occurred for the event defined for CAPEVT |
6 | DCBEVT2 | R | 0h | Latched Status Flag for Digital Compare Output B Event 2 0:Indicates no trip event has occurred on DCBEVT2 1:Indicates a trip event has occurred for the event defined for DCBEVT2 |
5 | DCBEVT1 | R | 0h | Latched Status Flag for Digital Compare Output B Event 1 0:Indicates no trip event has occurred on DCBEVT1 1:Indicates a trip event has occurred for the event defined for DCBEVT1 |
4 | DCAEVT2 | R | 0h | Latched Status Flag for Digital Compare Output A Event 2 0:Indicates no trip event has occurred on DCAEVT2 1:Indicates a trip event has occurred for the event defined for DCAEVT2 |
3 | DCAEVT1 | R | 0h | Latched Status Flag for Digital Compare Output A Event 1 0:Indicates no trip event has occurred on DCAEVT1 1:Indicates a trip event has occurred for the event defined for DCAEVT1 |
2 | OST | R | 0h | Latched Status Flag for A One-Shot Trip Event 0:No one-shot trip event has occurred. 1:Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by Writing the appropriate value to the TZCLR register. |
1 | CBC | R | 0h | Latched Status Flag for Cycle-By-Cycle Trip Event 0:No cycle-by-cycle trip event has occurred. 1:Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually cleared by the user. If the cycle-by-cycle trip event is still present when the CBC bit is cleared, then CBC will be immediately set again. The specified condition on the signal is automatically cleared when the EPWM time-base counter reaches zero [TBCTR = 0x00] if the trip condition is no longer present. The condition on the signal is only cleared when the TBCTR = 0x00 no matter where in the cycle the CBC flag is cleared. This bit is cleared by Writing the appropriate value to the TZCLR register. |
0 | INT | R | 0h | Latched Trip Interrupt Status Flag 0:Indicates no interrupt has been generated. 1:Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared. If the interrupt flag is cleared when either CBC or OST is set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. This bit is cleared by Writing the appropriate value to the TZCLR register. |