SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Trip Zone Clear Register.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 012Eh |
EPWM0_G1 | 5004 012Eh |
EPWM0_G2 | 5008 012Eh |
EPWM0_G3 | 500C 012Eh |
EPWM1_G0 | 5000 112Eh |
EPWM1_G1 | 5004 112Eh |
EPWM1_G2 | 5008 112Eh |
EPWM1_G3 | 500C 112Eh |
EPWM2_G0 | 5000 212Eh |
EPWM2_G1 | 5004 212Eh |
EPWM2_G2 | 5008 212Eh |
EPWM2_G3 | 500C 212Eh |
EPWM3_G0 | 5000 312Eh |
EPWM3_G1 | 5004 312Eh |
EPWM3_G2 | 5008 312Eh |
EPWM3_G3 | 500C 312Eh |
EPWM4_G0 | 5000 412Eh |
EPWM4_G1 | 5004 412Eh |
EPWM4_G2 | 5008 412Eh |
EPWM4_G3 | 500C 412Eh |
EPWM5_G0 | 5000 512Eh |
EPWM5_G1 | 5004 512Eh |
EPWM5_G2 | 5008 512Eh |
EPWM5_G3 | 500C 512Eh |
EPWM6_G0 | 5000 612Eh |
EPWM6_G1 | 5004 612Eh |
EPWM6_G2 | 5008 612Eh |
EPWM6_G3 | 500C 612Eh |
EPWM7_G0 | 5000 712Eh |
EPWM7_G1 | 5004 712Eh |
EPWM7_G2 | 5008 712Eh |
EPWM7_G3 | 500C 712Eh |
EPWM8_G0 | 5000 812Eh |
EPWM8_G1 | 5004 812Eh |
EPWM8_G2 | 5008 812Eh |
EPWM8_G3 | 500C 812Eh |
EPWM9_G0 | 5000 912Eh |
EPWM9_G1 | 5004 912Eh |
EPWM9_G2 | 5008 912Eh |
EPWM9_G3 | 500C 912Eh |
EPWM10_G0 | 5000 A12Eh |
EPWM10_G1 | 5004 A12Eh |
EPWM10_G2 | 5008 A12Eh |
EPWM10_G3 | 500C A12Eh |
EPWM11_G0 | 5000 B12Eh |
EPWM11_G1 | 5004 B12Eh |
EPWM11_G2 | 5008 B12Eh |
EPWM11_G3 | 500C B12Eh |
EPWM12_G0 | 5000 C12Eh |
EPWM12_G1 | 5004 C12Eh |
EPWM12_G2 | 5008 C12Eh |
EPWM12_G3 | 500C C12Eh |
EPWM13_G0 | 5000 D12Eh |
EPWM13_G1 | 5004 D12Eh |
EPWM13_G2 | 5008 D12Eh |
EPWM13_G3 | 500C D12Eh |
EPWM14_G0 | 5000 E12Eh |
EPWM14_G1 | 5004 E12Eh |
EPWM14_G2 | 5008 E12Eh |
EPWM14_G3 | 500C E12Eh |
EPWM15_G0 | 5000 F12Eh |
EPWM15_G1 | 5004 F12Eh |
EPWM15_G2 | 5008 F12Eh |
EPWM15_G3 | 500C F12Eh |
EPWM16_G0 | 5001 012Eh |
EPWM16_G1 | 5005 012Eh |
EPWM16_G2 | 5009 012Eh |
EPWM16_G3 | 500D 012Eh |
EPWM17_G0 | 5001 112Eh |
EPWM17_G1 | 5005 112Eh |
EPWM17_G2 | 5009 112Eh |
EPWM17_G3 | 500D 112Eh |
EPWM18_G0 | 5001 212Eh |
EPWM18_G1 | 5005 212Eh |
EPWM18_G2 | 5009 212Eh |
EPWM18_G3 | 500D 212Eh |
EPWM19_G0 | 5001 312Eh |
EPWM19_G1 | 5005 312Eh |
EPWM19_G2 | 5009 312Eh |
EPWM19_G3 | 500D 312Eh |
EPWM20_G0 | 5001 412Eh |
EPWM20_G1 | 5005 412Eh |
EPWM20_G2 | 5009 412Eh |
EPWM20_G3 | 500D 412Eh |
EPWM21_G0 | 5001 512Eh |
EPWM21_G1 | 5005 512Eh |
EPWM21_G2 | 5009 512Eh |
EPWM21_G3 | 500D 512Eh |
EPWM22_G0 | 5001 612Eh |
EPWM22_G1 | 5005 612Eh |
EPWM22_G2 | 5009 612Eh |
EPWM22_G3 | 500D 612Eh |
EPWM23_G0 | 5001 712Eh |
EPWM23_G1 | 5005 712Eh |
EPWM23_G2 | 5009 712Eh |
EPWM23_G3 | 500D 712Eh |
EPWM24_G0 | 5001 812Eh |
EPWM24_G1 | 5005 812Eh |
EPWM24_G2 | 5009 812Eh |
EPWM24_G3 | 500D 812Eh |
EPWM25_G0 | 5001 912Eh |
EPWM25_G1 | 5005 912Eh |
EPWM25_G2 | 5009 912Eh |
EPWM25_G3 | 500D 912Eh |
EPWM26_G0 | 5001 A12Eh |
EPWM26_G1 | 5005 A12Eh |
EPWM26_G2 | 5009 A12Eh |
EPWM26_G3 | 500D A12Eh |
EPWM27_G0 | 5001 B12Eh |
EPWM27_G1 | 5005 B12Eh |
EPWM27_G2 | 5009 B12Eh |
EPWM27_G3 | 500D B12Eh |
EPWM28_G0 | 5001 C12Eh |
EPWM28_G1 | 5005 C12Eh |
EPWM28_G2 | 5009 C12Eh |
EPWM28_G3 | 500D C12Eh |
EPWM29_G0 | 5001 D12Eh |
EPWM29_G1 | 5005 D12Eh |
EPWM29_G2 | 5009 D12Eh |
EPWM29_G3 | 500D D12Eh |
EPWM30_G0 | 5001 E12Eh |
EPWM30_G1 | 5005 E12Eh |
EPWM30_G2 | 5009 E12Eh |
EPWM30_G3 | 500D E12Eh |
EPWM31_G0 | 5001 F12Eh |
EPWM31_G1 | 5005 F12Eh |
EPWM31_G2 | 5009 F12Eh |
EPWM31_G3 | 500D F12Eh |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CBCPULSE | RESERVED_1 | ||||||
R/W | R | ||||||
0h | 0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPEVT | DCBEVT2 | DCBEVT1 | DCAEVT2 | DCAEVT1 | OST | CBC | INT |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | CBCPULSE | R/W | 0h | Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00:CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01:CTR = PRD pulse clears CBC trip latch. 10:CTR = zero or CTR = PRD pulse clears CBC trip latch. 11:CBC trip latch is not cleared |
13:8 | RESERVED_1 | R | 0h | Reserved |
7 | CAPEVT | R/W1TS | 0h | Clear Flag for Capture Event 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the CAPEVT event trip condition. |
6 | DCBEVT2 | R/W1TS | 0h | Clear Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT2 event trip condition. |
5 | DCBEVT1 | R/W1TS | 0h | Clear Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCBEVT1 event trip condition. |
4 | DCAEVT2 | R/W1TS | 0h | Clear Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT2 event trip condition. |
3 | DCAEVT1 | R/W1TS | 0h | Clear Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 clears the DCAEVT1 event trip condition. |
2 | OST | R/W1TS | 0h | Clear Flag for One-Shot Trip [OST] Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition. |
1 | CBC | R/W1TS | 0h | Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0:Has no effect. Always reads back a 0. 1:Clears this Trip [set] condition. |
0 | INT | R/W1TS | 0h | Global Interrupt Clear Flag 0:Has no effect. Always reads back a 0. 1:Clears the trip-interrupt flag for this EPWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit is cleared and any of the other flag bits are set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. |