SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Event-Trigger Mixed INT Selection.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 016Ch |
EPWM0_G1 | 5004 016Ch |
EPWM0_G2 | 5008 016Ch |
EPWM0_G3 | 500C 016Ch |
EPWM1_G0 | 5000 116Ch |
EPWM1_G1 | 5004 116Ch |
EPWM1_G2 | 5008 116Ch |
EPWM1_G3 | 500C 116Ch |
EPWM2_G0 | 5000 216Ch |
EPWM2_G1 | 5004 216Ch |
EPWM2_G2 | 5008 216Ch |
EPWM2_G3 | 500C 216Ch |
EPWM3_G0 | 5000 316Ch |
EPWM3_G1 | 5004 316Ch |
EPWM3_G2 | 5008 316Ch |
EPWM3_G3 | 500C 316Ch |
EPWM4_G0 | 5000 416Ch |
EPWM4_G1 | 5004 416Ch |
EPWM4_G2 | 5008 416Ch |
EPWM4_G3 | 500C 416Ch |
EPWM5_G0 | 5000 516Ch |
EPWM5_G1 | 5004 516Ch |
EPWM5_G2 | 5008 516Ch |
EPWM5_G3 | 500C 516Ch |
EPWM6_G0 | 5000 616Ch |
EPWM6_G1 | 5004 616Ch |
EPWM6_G2 | 5008 616Ch |
EPWM6_G3 | 500C 616Ch |
EPWM7_G0 | 5000 716Ch |
EPWM7_G1 | 5004 716Ch |
EPWM7_G2 | 5008 716Ch |
EPWM7_G3 | 500C 716Ch |
EPWM8_G0 | 5000 816Ch |
EPWM8_G1 | 5004 816Ch |
EPWM8_G2 | 5008 816Ch |
EPWM8_G3 | 500C 816Ch |
EPWM9_G0 | 5000 916Ch |
EPWM9_G1 | 5004 916Ch |
EPWM9_G2 | 5008 916Ch |
EPWM9_G3 | 500C 916Ch |
EPWM10_G0 | 5000 A16Ch |
EPWM10_G1 | 5004 A16Ch |
EPWM10_G2 | 5008 A16Ch |
EPWM10_G3 | 500C A16Ch |
EPWM11_G0 | 5000 B16Ch |
EPWM11_G1 | 5004 B16Ch |
EPWM11_G2 | 5008 B16Ch |
EPWM11_G3 | 500C B16Ch |
EPWM12_G0 | 5000 C16Ch |
EPWM12_G1 | 5004 C16Ch |
EPWM12_G2 | 5008 C16Ch |
EPWM12_G3 | 500C C16Ch |
EPWM13_G0 | 5000 D16Ch |
EPWM13_G1 | 5004 D16Ch |
EPWM13_G2 | 5008 D16Ch |
EPWM13_G3 | 500C D16Ch |
EPWM14_G0 | 5000 E16Ch |
EPWM14_G1 | 5004 E16Ch |
EPWM14_G2 | 5008 E16Ch |
EPWM14_G3 | 500C E16Ch |
EPWM15_G0 | 5000 F16Ch |
EPWM15_G1 | 5004 F16Ch |
EPWM15_G2 | 5008 F16Ch |
EPWM15_G3 | 500C F16Ch |
EPWM16_G0 | 5001 016Ch |
EPWM16_G1 | 5005 016Ch |
EPWM16_G2 | 5009 016Ch |
EPWM16_G3 | 500D 016Ch |
EPWM17_G0 | 5001 116Ch |
EPWM17_G1 | 5005 116Ch |
EPWM17_G2 | 5009 116Ch |
EPWM17_G3 | 500D 116Ch |
EPWM18_G0 | 5001 216Ch |
EPWM18_G1 | 5005 216Ch |
EPWM18_G2 | 5009 216Ch |
EPWM18_G3 | 500D 216Ch |
EPWM19_G0 | 5001 316Ch |
EPWM19_G1 | 5005 316Ch |
EPWM19_G2 | 5009 316Ch |
EPWM19_G3 | 500D 316Ch |
EPWM20_G0 | 5001 416Ch |
EPWM20_G1 | 5005 416Ch |
EPWM20_G2 | 5009 416Ch |
EPWM20_G3 | 500D 416Ch |
EPWM21_G0 | 5001 516Ch |
EPWM21_G1 | 5005 516Ch |
EPWM21_G2 | 5009 516Ch |
EPWM21_G3 | 500D 516Ch |
EPWM22_G0 | 5001 616Ch |
EPWM22_G1 | 5005 616Ch |
EPWM22_G2 | 5009 616Ch |
EPWM22_G3 | 500D 616Ch |
EPWM23_G0 | 5001 716Ch |
EPWM23_G1 | 5005 716Ch |
EPWM23_G2 | 5009 716Ch |
EPWM23_G3 | 500D 716Ch |
EPWM24_G0 | 5001 816Ch |
EPWM24_G1 | 5005 816Ch |
EPWM24_G2 | 5009 816Ch |
EPWM24_G3 | 500D 816Ch |
EPWM25_G0 | 5001 916Ch |
EPWM25_G1 | 5005 916Ch |
EPWM25_G2 | 5009 916Ch |
EPWM25_G3 | 500D 916Ch |
EPWM26_G0 | 5001 A16Ch |
EPWM26_G1 | 5005 A16Ch |
EPWM26_G2 | 5009 A16Ch |
EPWM26_G3 | 500D A16Ch |
EPWM27_G0 | 5001 B16Ch |
EPWM27_G1 | 5005 B16Ch |
EPWM27_G2 | 5009 B16Ch |
EPWM27_G3 | 500D B16Ch |
EPWM28_G0 | 5001 C16Ch |
EPWM28_G1 | 5005 C16Ch |
EPWM28_G2 | 5009 C16Ch |
EPWM28_G3 | 500D C16Ch |
EPWM29_G0 | 5001 D16Ch |
EPWM29_G1 | 5005 D16Ch |
EPWM29_G2 | 5009 D16Ch |
EPWM29_G3 | 500D D16Ch |
EPWM30_G0 | 5001 E16Ch |
EPWM30_G1 | 5005 E16Ch |
EPWM30_G2 | 5009 E16Ch |
EPWM30_G3 | 500D E16Ch |
EPWM31_G0 | 5001 F16Ch |
EPWM31_G1 | 5005 F16Ch |
EPWM31_G2 | 5009 F16Ch |
EPWM31_G3 | 500D F16Ch |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_1 | DCAEVT1 | CDD | CDU | ||||
R | R/W | R/W | R/W | ||||
0h | 0h | 0h | 0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCD | CCU | CBD | CBU | CAD | CAU | PRD | ZRO |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
0h | 0h | 0h | 0h | 0h | 0h | 1h | 1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:11 | RESERVED_1 | R | 0h | Reserved |
10 | DCAEVT1 | R/W | 0h | Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0:DCAEVT1.soc event is not enabled 1:Enable DCAEVT1.soc event |
9 | CDD | R/W | 0h | Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD down-count match enable event is not enabled 1:Enable CMPD down-count match enable event |
8 | CDU | R/W | 0h | Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPD up-count match enable event is not enabled 1:Enable CMPD up-count match enable event |
7 | CCD | R/W | 0h | Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC down-count match enable event is not enabled 1:Enable CMPC down-count match enable event |
6 | CCU | R/W | 0h | Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPC up-count match enable event is not enabled 1:Enable CMPC up-count match enable event |
5 | CBD | R/W | 0h | Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB down-count match enable event is not enabled 1:Enable CMPB down-count match enable event |
4 | CBU | R/W | 0h | Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPB up-count match enable event is not enabled 1:Enable CMPB up-count match enable event |
3 | CAD | R/W | 0h | Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA down-count match enable event is not enabled 1:Enable CMPA down-count match enable event |
2 | CAU | R/W | 0h | Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0:CMPA up-count match enable event is not enabled 1:Enable CMPA up-count match enable event |
1 | PRD | R/W | 1h | Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Period match event is not enabled 1:Enable period match event |
0 | ZRO | R/W | 1h | Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0:Zero match event is not enabled 1:Enable zero match event |