SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Digital Compare Capture Control Register.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0190h |
EPWM0_G1 | 5004 0190h |
EPWM0_G2 | 5008 0190h |
EPWM0_G3 | 500C 0190h |
EPWM1_G0 | 5000 1190h |
EPWM1_G1 | 5004 1190h |
EPWM1_G2 | 5008 1190h |
EPWM1_G3 | 500C 1190h |
EPWM2_G0 | 5000 2190h |
EPWM2_G1 | 5004 2190h |
EPWM2_G2 | 5008 2190h |
EPWM2_G3 | 500C 2190h |
EPWM3_G0 | 5000 3190h |
EPWM3_G1 | 5004 3190h |
EPWM3_G2 | 5008 3190h |
EPWM3_G3 | 500C 3190h |
EPWM4_G0 | 5000 4190h |
EPWM4_G1 | 5004 4190h |
EPWM4_G2 | 5008 4190h |
EPWM4_G3 | 500C 4190h |
EPWM5_G0 | 5000 5190h |
EPWM5_G1 | 5004 5190h |
EPWM5_G2 | 5008 5190h |
EPWM5_G3 | 500C 5190h |
EPWM6_G0 | 5000 6190h |
EPWM6_G1 | 5004 6190h |
EPWM6_G2 | 5008 6190h |
EPWM6_G3 | 500C 6190h |
EPWM7_G0 | 5000 7190h |
EPWM7_G1 | 5004 7190h |
EPWM7_G2 | 5008 7190h |
EPWM7_G3 | 500C 7190h |
EPWM8_G0 | 5000 8190h |
EPWM8_G1 | 5004 8190h |
EPWM8_G2 | 5008 8190h |
EPWM8_G3 | 500C 8190h |
EPWM9_G0 | 5000 9190h |
EPWM9_G1 | 5004 9190h |
EPWM9_G2 | 5008 9190h |
EPWM9_G3 | 500C 9190h |
EPWM10_G0 | 5000 A190h |
EPWM10_G1 | 5004 A190h |
EPWM10_G2 | 5008 A190h |
EPWM10_G3 | 500C A190h |
EPWM11_G0 | 5000 B190h |
EPWM11_G1 | 5004 B190h |
EPWM11_G2 | 5008 B190h |
EPWM11_G3 | 500C B190h |
EPWM12_G0 | 5000 C190h |
EPWM12_G1 | 5004 C190h |
EPWM12_G2 | 5008 C190h |
EPWM12_G3 | 500C C190h |
EPWM13_G0 | 5000 D190h |
EPWM13_G1 | 5004 D190h |
EPWM13_G2 | 5008 D190h |
EPWM13_G3 | 500C D190h |
EPWM14_G0 | 5000 E190h |
EPWM14_G1 | 5004 E190h |
EPWM14_G2 | 5008 E190h |
EPWM14_G3 | 500C E190h |
EPWM15_G0 | 5000 F190h |
EPWM15_G1 | 5004 F190h |
EPWM15_G2 | 5008 F190h |
EPWM15_G3 | 500C F190h |
EPWM16_G0 | 5001 0190h |
EPWM16_G1 | 5005 0190h |
EPWM16_G2 | 5009 0190h |
EPWM16_G3 | 500D 0190h |
EPWM17_G0 | 5001 1190h |
EPWM17_G1 | 5005 1190h |
EPWM17_G2 | 5009 1190h |
EPWM17_G3 | 500D 1190h |
EPWM18_G0 | 5001 2190h |
EPWM18_G1 | 5005 2190h |
EPWM18_G2 | 5009 2190h |
EPWM18_G3 | 500D 2190h |
EPWM19_G0 | 5001 3190h |
EPWM19_G1 | 5005 3190h |
EPWM19_G2 | 5009 3190h |
EPWM19_G3 | 500D 3190h |
EPWM20_G0 | 5001 4190h |
EPWM20_G1 | 5005 4190h |
EPWM20_G2 | 5009 4190h |
EPWM20_G3 | 500D 4190h |
EPWM21_G0 | 5001 5190h |
EPWM21_G1 | 5005 5190h |
EPWM21_G2 | 5009 5190h |
EPWM21_G3 | 500D 5190h |
EPWM22_G0 | 5001 6190h |
EPWM22_G1 | 5005 6190h |
EPWM22_G2 | 5009 6190h |
EPWM22_G3 | 500D 6190h |
EPWM23_G0 | 5001 7190h |
EPWM23_G1 | 5005 7190h |
EPWM23_G2 | 5009 7190h |
EPWM23_G3 | 500D 7190h |
EPWM24_G0 | 5001 8190h |
EPWM24_G1 | 5005 8190h |
EPWM24_G2 | 5009 8190h |
EPWM24_G3 | 500D 8190h |
EPWM25_G0 | 5001 9190h |
EPWM25_G1 | 5005 9190h |
EPWM25_G2 | 5009 9190h |
EPWM25_G3 | 500D 9190h |
EPWM26_G0 | 5001 A190h |
EPWM26_G1 | 5005 A190h |
EPWM26_G2 | 5009 A190h |
EPWM26_G3 | 500D A190h |
EPWM27_G0 | 5001 B190h |
EPWM27_G1 | 5005 B190h |
EPWM27_G2 | 5009 B190h |
EPWM27_G3 | 500D B190h |
EPWM28_G0 | 5001 C190h |
EPWM28_G1 | 5005 C190h |
EPWM28_G2 | 5009 C190h |
EPWM28_G3 | 500D C190h |
EPWM29_G0 | 5001 D190h |
EPWM29_G1 | 5005 D190h |
EPWM29_G2 | 5009 D190h |
EPWM29_G3 | 500D D190h |
EPWM30_G0 | 5001 E190h |
EPWM30_G1 | 5005 E190h |
EPWM30_G2 | 5009 E190h |
EPWM30_G3 | 500D E190h |
EPWM31_G0 | 5001 F190h |
EPWM31_G1 | 5005 F190h |
EPWM31_G2 | 5009 F190h |
EPWM31_G3 | 500D F190h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CAPMODE | CAPCLR | CAPSTS | RESERVED_1 | ||||
R/W | R/W1TS | R | R | ||||
0h | 0h | 0h | 0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | SHDWMODE | CAPE | |||||
R | R/W | R/W | |||||
0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | CAPMODE | R/W | 0h | Counter Capture Mode 0:When a DCEVTFILT occurs and the counter capture is enabled, then the current TBCNT value is captured in the active register. When the respective trip event occurs, further trip [capture] events are ignored until the next PRD_eq or CNT_zero event [as selected by the PULSESEL bit in the DCFCTL register] re-triggers the capture mechanism. If active mode is enabled, via SHDWMODE bit in DCC0PCTL register, CPU reads of this register will return the active register value. If shadow mode is enabled, via SHDWMODE bit in DCC0PCTL register, the active register is copied to the shadow register on the PRD_eq or CNT_zero event [whichever is selected by PULSESEL bit in DCFCTL register]. CPU reads of this register will return the shadow register value. 1:When a DCEVTFILT occurs and the counter capture is enabled, then the current TBCNT value is captured in the active register. When the respective trip event occurs - it will set the CAPSTS flag and further trip [capture] events are ignored until this bit is cleared. CAPSTS can be cleared by writing to CAPCLR bit in DCC0PCTL register and it re-triggers the capture mechanism. If active mode is enabled, via SHDWMODE bit in DCC0PCTL register, CPU reads of this register will return the active register value. If shadow mode is enabled, via SHDWMODE bit in DCC0PCTL register, the active register is copied to the shadow register on the PRD_eq or CNT_zero event [whichever is selected by PULSESEL bit in DCFCTL register]. CPU reads of this register will return the shadow register value. |
14 | CAPCLR | R/W1TS | 0h | DC Capture Latched Status Clear Flag 0:Writing a 0 has no effect. 1:Writing a 1 will clear this CAPSTS [set] condition. |
13 | CAPSTS | R | 0h | Latched Status Flag for Capture Event 0:No DC capture event occurred. 1:A DC capture event has occurred. |
12:2 | RESERVED_1 | R | 0h | Reserved |
1 | SHDWMODE | R/W | 0h | TBCTR Counter Capture Shadow Select Mode 0:Enable shadow mode. The DCC0P active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCC0P register will return the shadow register contents. 1:Active Mode. In this mode the shadow register is disabled. CPU reads from the DCC0P register will always return the active register contents. |
0 | CAPE | R/W | 0h | TBCTR Counter Capture Enable/Disable 0:Disable the time-base counter capture. 1:Enable the time-base counter capture. |