SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Digital Compare Counter Capture Register .
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 019Eh |
EPWM0_G1 | 5004 019Eh |
EPWM0_G2 | 5008 019Eh |
EPWM0_G3 | 500C 019Eh |
EPWM1_G0 | 5000 119Eh |
EPWM1_G1 | 5004 119Eh |
EPWM1_G2 | 5008 119Eh |
EPWM1_G3 | 500C 119Eh |
EPWM2_G0 | 5000 219Eh |
EPWM2_G1 | 5004 219Eh |
EPWM2_G2 | 5008 219Eh |
EPWM2_G3 | 500C 219Eh |
EPWM3_G0 | 5000 319Eh |
EPWM3_G1 | 5004 319Eh |
EPWM3_G2 | 5008 319Eh |
EPWM3_G3 | 500C 319Eh |
EPWM4_G0 | 5000 419Eh |
EPWM4_G1 | 5004 419Eh |
EPWM4_G2 | 5008 419Eh |
EPWM4_G3 | 500C 419Eh |
EPWM5_G0 | 5000 519Eh |
EPWM5_G1 | 5004 519Eh |
EPWM5_G2 | 5008 519Eh |
EPWM5_G3 | 500C 519Eh |
EPWM6_G0 | 5000 619Eh |
EPWM6_G1 | 5004 619Eh |
EPWM6_G2 | 5008 619Eh |
EPWM6_G3 | 500C 619Eh |
EPWM7_G0 | 5000 719Eh |
EPWM7_G1 | 5004 719Eh |
EPWM7_G2 | 5008 719Eh |
EPWM7_G3 | 500C 719Eh |
EPWM8_G0 | 5000 819Eh |
EPWM8_G1 | 5004 819Eh |
EPWM8_G2 | 5008 819Eh |
EPWM8_G3 | 500C 819Eh |
EPWM9_G0 | 5000 919Eh |
EPWM9_G1 | 5004 919Eh |
EPWM9_G2 | 5008 919Eh |
EPWM9_G3 | 500C 919Eh |
EPWM10_G0 | 5000 A19Eh |
EPWM10_G1 | 5004 A19Eh |
EPWM10_G2 | 5008 A19Eh |
EPWM10_G3 | 500C A19Eh |
EPWM11_G0 | 5000 B19Eh |
EPWM11_G1 | 5004 B19Eh |
EPWM11_G2 | 5008 B19Eh |
EPWM11_G3 | 500C B19Eh |
EPWM12_G0 | 5000 C19Eh |
EPWM12_G1 | 5004 C19Eh |
EPWM12_G2 | 5008 C19Eh |
EPWM12_G3 | 500C C19Eh |
EPWM13_G0 | 5000 D19Eh |
EPWM13_G1 | 5004 D19Eh |
EPWM13_G2 | 5008 D19Eh |
EPWM13_G3 | 500C D19Eh |
EPWM14_G0 | 5000 E19Eh |
EPWM14_G1 | 5004 E19Eh |
EPWM14_G2 | 5008 E19Eh |
EPWM14_G3 | 500C E19Eh |
EPWM15_G0 | 5000 F19Eh |
EPWM15_G1 | 5004 F19Eh |
EPWM15_G2 | 5008 F19Eh |
EPWM15_G3 | 500C F19Eh |
EPWM16_G0 | 5001 019Eh |
EPWM16_G1 | 5005 019Eh |
EPWM16_G2 | 5009 019Eh |
EPWM16_G3 | 500D 019Eh |
EPWM17_G0 | 5001 119Eh |
EPWM17_G1 | 5005 119Eh |
EPWM17_G2 | 5009 119Eh |
EPWM17_G3 | 500D 119Eh |
EPWM18_G0 | 5001 219Eh |
EPWM18_G1 | 5005 219Eh |
EPWM18_G2 | 5009 219Eh |
EPWM18_G3 | 500D 219Eh |
EPWM19_G0 | 5001 319Eh |
EPWM19_G1 | 5005 319Eh |
EPWM19_G2 | 5009 319Eh |
EPWM19_G3 | 500D 319Eh |
EPWM20_G0 | 5001 419Eh |
EPWM20_G1 | 5005 419Eh |
EPWM20_G2 | 5009 419Eh |
EPWM20_G3 | 500D 419Eh |
EPWM21_G0 | 5001 519Eh |
EPWM21_G1 | 5005 519Eh |
EPWM21_G2 | 5009 519Eh |
EPWM21_G3 | 500D 519Eh |
EPWM22_G0 | 5001 619Eh |
EPWM22_G1 | 5005 619Eh |
EPWM22_G2 | 5009 619Eh |
EPWM22_G3 | 500D 619Eh |
EPWM23_G0 | 5001 719Eh |
EPWM23_G1 | 5005 719Eh |
EPWM23_G2 | 5009 719Eh |
EPWM23_G3 | 500D 719Eh |
EPWM24_G0 | 5001 819Eh |
EPWM24_G1 | 5005 819Eh |
EPWM24_G2 | 5009 819Eh |
EPWM24_G3 | 500D 819Eh |
EPWM25_G0 | 5001 919Eh |
EPWM25_G1 | 5005 919Eh |
EPWM25_G2 | 5009 919Eh |
EPWM25_G3 | 500D 919Eh |
EPWM26_G0 | 5001 A19Eh |
EPWM26_G1 | 5005 A19Eh |
EPWM26_G2 | 5009 A19Eh |
EPWM26_G3 | 500D A19Eh |
EPWM27_G0 | 5001 B19Eh |
EPWM27_G1 | 5005 B19Eh |
EPWM27_G2 | 5009 B19Eh |
EPWM27_G3 | 500D B19Eh |
EPWM28_G0 | 5001 C19Eh |
EPWM28_G1 | 5005 C19Eh |
EPWM28_G2 | 5009 C19Eh |
EPWM28_G3 | 500D C19Eh |
EPWM29_G0 | 5001 D19Eh |
EPWM29_G1 | 5005 D19Eh |
EPWM29_G2 | 5009 D19Eh |
EPWM29_G3 | 500D D19Eh |
EPWM30_G0 | 5001 E19Eh |
EPWM30_G1 | 5005 E19Eh |
EPWM30_G2 | 5009 E19Eh |
EPWM30_G3 | 500D E19Eh |
EPWM31_G0 | 5001 F19Eh |
EPWM31_G1 | 5005 F19Eh |
EPWM31_G2 | 5009 F19Eh |
EPWM31_G3 | 500D F19Eh |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DCCAP | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DCCAP | |||||||
R | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | DCCAP | R | 0h | Digital Compare Time-Base Counter Capture To enable time-base counter capture, set the DCC0PCLT[CAPE] bit to 1. If enabled, reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event. Further capture events are ignored until the next period or zero as selected by the DCFCTL[PULSESEL] bit. Shadowing of DCC0P is enabled and disabled by the DCC0PCTL[SHDWMODE] bit. By default this register is shadowed. - If DCC0PCTL[SHDWMODE] = 0, then the shadow is enabled. In this mode, the active register is copied to the shadow register on the TBCTR = TBPRD or TBCTR = zero as defined by the DCFCTL[PULSESEL] bit. CPU reads of this register will return the shadow register value. - If DCC0PCTL[SHDWMODE] = 1, then the shadow register is disabled. In this mode, CPU reads will return the active register value. The active and shadow registers share the same memory map address. |