SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
XCMP Mode Control Register.
Return to Summary Table
Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0400h |
EPWM0_G1 | 5004 0400h |
EPWM0_G2 | 5008 0400h |
EPWM0_G3 | 500C 0400h |
EPWM1_G0 | 5000 1400h |
EPWM1_G1 | 5004 1400h |
EPWM1_G2 | 5008 1400h |
EPWM1_G3 | 500C 1400h |
EPWM2_G0 | 5000 2400h |
EPWM2_G1 | 5004 2400h |
EPWM2_G2 | 5008 2400h |
EPWM2_G3 | 500C 2400h |
EPWM3_G0 | 5000 3400h |
EPWM3_G1 | 5004 3400h |
EPWM3_G2 | 5008 3400h |
EPWM3_G3 | 500C 3400h |
EPWM4_G0 | 5000 4400h |
EPWM4_G1 | 5004 4400h |
EPWM4_G2 | 5008 4400h |
EPWM4_G3 | 500C 4400h |
EPWM5_G0 | 5000 5400h |
EPWM5_G1 | 5004 5400h |
EPWM5_G2 | 5008 5400h |
EPWM5_G3 | 500C 5400h |
EPWM6_G0 | 5000 6400h |
EPWM6_G1 | 5004 6400h |
EPWM6_G2 | 5008 6400h |
EPWM6_G3 | 500C 6400h |
EPWM7_G0 | 5000 7400h |
EPWM7_G1 | 5004 7400h |
EPWM7_G2 | 5008 7400h |
EPWM7_G3 | 500C 7400h |
EPWM8_G0 | 5000 8400h |
EPWM8_G1 | 5004 8400h |
EPWM8_G2 | 5008 8400h |
EPWM8_G3 | 500C 8400h |
EPWM9_G0 | 5000 9400h |
EPWM9_G1 | 5004 9400h |
EPWM9_G2 | 5008 9400h |
EPWM9_G3 | 500C 9400h |
EPWM10_G0 | 5000 A400h |
EPWM10_G1 | 5004 A400h |
EPWM10_G2 | 5008 A400h |
EPWM10_G3 | 500C A400h |
EPWM11_G0 | 5000 B400h |
EPWM11_G1 | 5004 B400h |
EPWM11_G2 | 5008 B400h |
EPWM11_G3 | 500C B400h |
EPWM12_G0 | 5000 C400h |
EPWM12_G1 | 5004 C400h |
EPWM12_G2 | 5008 C400h |
EPWM12_G3 | 500C C400h |
EPWM13_G0 | 5000 D400h |
EPWM13_G1 | 5004 D400h |
EPWM13_G2 | 5008 D400h |
EPWM13_G3 | 500C D400h |
EPWM14_G0 | 5000 E400h |
EPWM14_G1 | 5004 E400h |
EPWM14_G2 | 5008 E400h |
EPWM14_G3 | 500C E400h |
EPWM15_G0 | 5000 F400h |
EPWM15_G1 | 5004 F400h |
EPWM15_G2 | 5008 F400h |
EPWM15_G3 | 500C F400h |
EPWM16_G0 | 5001 0400h |
EPWM16_G1 | 5005 0400h |
EPWM16_G2 | 5009 0400h |
EPWM16_G3 | 500D 0400h |
EPWM17_G0 | 5001 1400h |
EPWM17_G1 | 5005 1400h |
EPWM17_G2 | 5009 1400h |
EPWM17_G3 | 500D 1400h |
EPWM18_G0 | 5001 2400h |
EPWM18_G1 | 5005 2400h |
EPWM18_G2 | 5009 2400h |
EPWM18_G3 | 500D 2400h |
EPWM19_G0 | 5001 3400h |
EPWM19_G1 | 5005 3400h |
EPWM19_G2 | 5009 3400h |
EPWM19_G3 | 500D 3400h |
EPWM20_G0 | 5001 4400h |
EPWM20_G1 | 5005 4400h |
EPWM20_G2 | 5009 4400h |
EPWM20_G3 | 500D 4400h |
EPWM21_G0 | 5001 5400h |
EPWM21_G1 | 5005 5400h |
EPWM21_G2 | 5009 5400h |
EPWM21_G3 | 500D 5400h |
EPWM22_G0 | 5001 6400h |
EPWM22_G1 | 5005 6400h |
EPWM22_G2 | 5009 6400h |
EPWM22_G3 | 500D 6400h |
EPWM23_G0 | 5001 7400h |
EPWM23_G1 | 5005 7400h |
EPWM23_G2 | 5009 7400h |
EPWM23_G3 | 500D 7400h |
EPWM24_G0 | 5001 8400h |
EPWM24_G1 | 5005 8400h |
EPWM24_G2 | 5009 8400h |
EPWM24_G3 | 500D 8400h |
EPWM25_G0 | 5001 9400h |
EPWM25_G1 | 5005 9400h |
EPWM25_G2 | 5009 9400h |
EPWM25_G3 | 500D 9400h |
EPWM26_G0 | 5001 A400h |
EPWM26_G1 | 5005 A400h |
EPWM26_G2 | 5009 A400h |
EPWM26_G3 | 500D A400h |
EPWM27_G0 | 5001 B400h |
EPWM27_G1 | 5005 B400h |
EPWM27_G2 | 5009 B400h |
EPWM27_G3 | 500D B400h |
EPWM28_G0 | 5001 C400h |
EPWM28_G1 | 5005 C400h |
EPWM28_G2 | 5009 C400h |
EPWM28_G3 | 500D C400h |
EPWM29_G0 | 5001 D400h |
EPWM29_G1 | 5005 D400h |
EPWM29_G2 | 5009 D400h |
EPWM29_G3 | 500D D400h |
EPWM30_G0 | 5001 E400h |
EPWM30_G1 | 5005 E400h |
EPWM30_G2 | 5009 E400h |
EPWM30_G3 | 500D E400h |
EPWM31_G0 | 5001 F400h |
EPWM31_G1 | 5005 F400h |
EPWM31_G2 | 5009 F400h |
EPWM31_G3 | 500D F400h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED_2 | |||||||
R | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED_2 | |||||||
R | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_2 | XCMPB_ALLOC | ||||||
R | R/W | ||||||
0h | 0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
XCMPA_ALLOC | RESERVED_1 | XCMPSPLIT | XCMPEN | ||||
R/W | R | R/W | R/W | ||||
0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:12 | RESERVED_2 | R | 0h | Reserved |
11:8 | XCMPB_ALLOC | R/W | 0h | XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5, XCMP6 - 7 --> XCMP5, XCMP6, XCMP7 - 8 --> XCMP5, XCMP6, XCMP7, XCMP8 This register settings will take effect only when XCMPEN==1 And XCMPSPLIT ==1 |
7:4 | XCMPA_ALLOC | R/W | 0h | XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1, XCMP2 - 3 --> XCMP1, XCMP2, XCMP3 - 4 --> XCMP1, XCMP2, XCMP3, XCMP4 - 5 --> XCMP1, XCMP2, XCMP3, XCMP4, XCMP5 - 6 --> XCMP1, XCMP2, XCMP3, XCMP4, XCMP5, XCMP6 - 7 --> XCMP1, XCMP2, XCMP3, XCMP4, XCMP5, XCMP6, XCMP7 - 8 --> XCMP1, XCMP2, XCMP3, XCMP4, XCMP5, XCMP6, XCMP7, XCMP8 This register settings will take effect only when XCMPEN==1 If XCMPSPLIT ==1, this field cannot be greater than 4. If XCMPSPLIT ==1 only lower 3 bits are used in this field. |
3:2 | RESERVED_1 | R | 0h | Reserved |
1 | XCMPSPLIT | R/W | 0h | XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA, XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1 |
0 | XCMPEN | R/W | 0h | XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation] |