SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
XCMP Mode Load Control Register.
Return to Summary Table
Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0410h |
EPWM0_G1 | 5004 0410h |
EPWM0_G2 | 5008 0410h |
EPWM0_G3 | 500C 0410h |
EPWM1_G0 | 5000 1410h |
EPWM1_G1 | 5004 1410h |
EPWM1_G2 | 5008 1410h |
EPWM1_G3 | 500C 1410h |
EPWM2_G0 | 5000 2410h |
EPWM2_G1 | 5004 2410h |
EPWM2_G2 | 5008 2410h |
EPWM2_G3 | 500C 2410h |
EPWM3_G0 | 5000 3410h |
EPWM3_G1 | 5004 3410h |
EPWM3_G2 | 5008 3410h |
EPWM3_G3 | 500C 3410h |
EPWM4_G0 | 5000 4410h |
EPWM4_G1 | 5004 4410h |
EPWM4_G2 | 5008 4410h |
EPWM4_G3 | 500C 4410h |
EPWM5_G0 | 5000 5410h |
EPWM5_G1 | 5004 5410h |
EPWM5_G2 | 5008 5410h |
EPWM5_G3 | 500C 5410h |
EPWM6_G0 | 5000 6410h |
EPWM6_G1 | 5004 6410h |
EPWM6_G2 | 5008 6410h |
EPWM6_G3 | 500C 6410h |
EPWM7_G0 | 5000 7410h |
EPWM7_G1 | 5004 7410h |
EPWM7_G2 | 5008 7410h |
EPWM7_G3 | 500C 7410h |
EPWM8_G0 | 5000 8410h |
EPWM8_G1 | 5004 8410h |
EPWM8_G2 | 5008 8410h |
EPWM8_G3 | 500C 8410h |
EPWM9_G0 | 5000 9410h |
EPWM9_G1 | 5004 9410h |
EPWM9_G2 | 5008 9410h |
EPWM9_G3 | 500C 9410h |
EPWM10_G0 | 5000 A410h |
EPWM10_G1 | 5004 A410h |
EPWM10_G2 | 5008 A410h |
EPWM10_G3 | 500C A410h |
EPWM11_G0 | 5000 B410h |
EPWM11_G1 | 5004 B410h |
EPWM11_G2 | 5008 B410h |
EPWM11_G3 | 500C B410h |
EPWM12_G0 | 5000 C410h |
EPWM12_G1 | 5004 C410h |
EPWM12_G2 | 5008 C410h |
EPWM12_G3 | 500C C410h |
EPWM13_G0 | 5000 D410h |
EPWM13_G1 | 5004 D410h |
EPWM13_G2 | 5008 D410h |
EPWM13_G3 | 500C D410h |
EPWM14_G0 | 5000 E410h |
EPWM14_G1 | 5004 E410h |
EPWM14_G2 | 5008 E410h |
EPWM14_G3 | 500C E410h |
EPWM15_G0 | 5000 F410h |
EPWM15_G1 | 5004 F410h |
EPWM15_G2 | 5008 F410h |
EPWM15_G3 | 500C F410h |
EPWM16_G0 | 5001 0410h |
EPWM16_G1 | 5005 0410h |
EPWM16_G2 | 5009 0410h |
EPWM16_G3 | 500D 0410h |
EPWM17_G0 | 5001 1410h |
EPWM17_G1 | 5005 1410h |
EPWM17_G2 | 5009 1410h |
EPWM17_G3 | 500D 1410h |
EPWM18_G0 | 5001 2410h |
EPWM18_G1 | 5005 2410h |
EPWM18_G2 | 5009 2410h |
EPWM18_G3 | 500D 2410h |
EPWM19_G0 | 5001 3410h |
EPWM19_G1 | 5005 3410h |
EPWM19_G2 | 5009 3410h |
EPWM19_G3 | 500D 3410h |
EPWM20_G0 | 5001 4410h |
EPWM20_G1 | 5005 4410h |
EPWM20_G2 | 5009 4410h |
EPWM20_G3 | 500D 4410h |
EPWM21_G0 | 5001 5410h |
EPWM21_G1 | 5005 5410h |
EPWM21_G2 | 5009 5410h |
EPWM21_G3 | 500D 5410h |
EPWM22_G0 | 5001 6410h |
EPWM22_G1 | 5005 6410h |
EPWM22_G2 | 5009 6410h |
EPWM22_G3 | 500D 6410h |
EPWM23_G0 | 5001 7410h |
EPWM23_G1 | 5005 7410h |
EPWM23_G2 | 5009 7410h |
EPWM23_G3 | 500D 7410h |
EPWM24_G0 | 5001 8410h |
EPWM24_G1 | 5005 8410h |
EPWM24_G2 | 5009 8410h |
EPWM24_G3 | 500D 8410h |
EPWM25_G0 | 5001 9410h |
EPWM25_G1 | 5005 9410h |
EPWM25_G2 | 5009 9410h |
EPWM25_G3 | 500D 9410h |
EPWM26_G0 | 5001 A410h |
EPWM26_G1 | 5005 A410h |
EPWM26_G2 | 5009 A410h |
EPWM26_G3 | 500D A410h |
EPWM27_G0 | 5001 B410h |
EPWM27_G1 | 5005 B410h |
EPWM27_G2 | 5009 B410h |
EPWM27_G3 | 500D B410h |
EPWM28_G0 | 5001 C410h |
EPWM28_G1 | 5005 C410h |
EPWM28_G2 | 5009 C410h |
EPWM28_G3 | 500D C410h |
EPWM29_G0 | 5001 D410h |
EPWM29_G1 | 5005 D410h |
EPWM29_G2 | 5009 D410h |
EPWM29_G3 | 500D D410h |
EPWM30_G0 | 5001 E410h |
EPWM30_G1 | 5005 E410h |
EPWM30_G2 | 5009 E410h |
EPWM30_G3 | 500D E410h |
EPWM31_G0 | 5001 F410h |
EPWM31_G1 | 5005 F410h |
EPWM31_G2 | 5009 F410h |
EPWM31_G3 | 500D F410h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED_8 | RPTBUF3CNT | RESERVED_7 | RPTBUF3PRD | ||||
R | R | R | R/W | ||||
0h | 0h | 0h | 0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED_6 | RPTBUF2CNT | RESERVED_5 | RPTBUF2PRD | ||||
R | R | R | R/W | ||||
0h | 0h | 0h | 0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_4 | SHDWBUFPTR_LOADMULTIPLE | SHDWBUFPTR_LOADONCE | |||||
R | R | R/W | |||||
0h | 0h | 0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_3 | SHDWLEVEL | RESERVED_2 | LOADMODE | RESERVED_1 | |||
R | R/W | R | R/W | R | |||
0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED_8 | R | 0h | Reserved |
30:28 | RPTBUF3CNT | R | 0h | Repeat Count Status Shadow Buffer 3:These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I,e, shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001 Shadow buffer applied twice on 2 successive load strobes 3'b010 Shadow buffer applied thrice on 3 successive load strobes . . 3'b111 Shadow buffer applied 8 times on 8 successive load strobes These bits reset to zero every time STARTLD is initiated. |
27 | RESERVED_7 | R | 0h | Reserved |
26:24 | RPTBUF3PRD | R/W | 0h | Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I,e, shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load pulse 3'b001 Apply shadow buffer twice on 2 successive load strobes and move to the next shadow buffer on the following load pulse 3'b010 Apply shadow buffer thrice on 3 successive load strobes and move to the next shadow buffer on the following load pulse . . 3'b111 Apply shadow buffer 8 times on 8 successive load strobes and move to the next shadow buffer on the following load pulse |
23 | RESERVED_6 | R | 0h | Reserved |
22:20 | RPTBUF2CNT | R | 0h | Repeat Count Status Shadow Buffer 2:These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I,e, shadow buffer 1. 3'b000 Shadow buffer reset value with STARTLD and copied to Active register 3'b001 Shadow buffer applied twice on 2 successive load strobes 3'b010 Shadow buffer applied thrice on 3 successive load strobes . . 3'b111 Shadow buffer applied 8 times on 8 successive load strobes These bits reset to zero every time STARTLD is initiated. |
19 | RESERVED_5 | R | 0h | Reserved |
18:16 | RPTBUF2PRD | R/W | 0h | Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I,e, shadow buffer 1. 3'b000 Apply shadow buffer once and move to the next shadow buffer on the following load pulse 3'b001 Apply shadow buffer twice on 2 successive load strobes and move to the next shadow buffer on the following load pulse 3'b010 Apply shadow buffer thrice on 3 successive load strobes and move to the next shadow buffer on the following load pulse . . 2'b12'b11 Apply shadow buffer 8 times on 8 successive load strobes and move to the next shadow buffer on the following load pulse |
15:12 | RESERVED_4 | R | 0h | Reserved |
11:10 | SHDWBUFPTR_LOADMULTIPLE | R | 0h | Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0,1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use |
9:8 | SHDWBUFPTR_LOADONCE | R/W | 0h | Register Load event count: These bits indicate the current shadow buffer in use. 2'b00 Reset value 0,1 1 Shadow buffer 1 in use 2'b10 2 Shadow buffer 2 in use 2'b11 3 Shadow buffer 3 in use |
7:6 | RESERVED_3 | R | 0h | Reserved |
5:4 | SHDWLEVEL | R/W | 0h | Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 2'b00 : XXXX Shadow level is set at zero. XXXX Active register is available 2'b01 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are available 2'b10 : XXXX Shadow level is set at 1. XXXX_SHDW1, XXXX_SHDW2 and Active registers are available 2'b11 : XXXX Shadow level is set at 1. XXXX_SHDW1, XXXX_SHDW2, XXXX_SHDW3 and Active registers are available |
3 | RESERVED_2 | R | 0h | Reserved |
2 | LOADMODE | R/W | 0h | Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe. SHDWBUFPTR is not automatically decremented in this case. User would set the SHDWBUFPTR for subsequent loads. 1 : [LOADMULTIPLE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWnActive registers. And STARTLD is cleared after SHDWLEVEL number of load strobes. SHDWBUFPTR decrements by 1 on a load strobe, until the SHDWBUFPTR reaches 1. |
1:0 | RESERVED_1 | R | 0h | Reserved |