SPRUJ51 june   2023

 

  1.   1
  2. 1Abstract
  3. 2EVM Revisions and Assembly Variants
    1. 2.1 Inside the Box
    2. 2.2 EMC, EMI and ESD Compliance
  4.   Trademarks
  5. 3System Description
    1. 3.1 Key Features
      1. 3.1.1 Processor
      2. 3.1.2 Power Supply
      3. 3.1.3 Memory
      4. 3.1.4 JTAG Emulator
      5. 3.1.5 Supported Interfaces and Peripherals
      6. 3.1.6 Expansion Connectors Headers to Support Application Specific Add On Boards
    2. 3.2 Functional Block Diagram
    3. 3.3 AM62x-Low Power SK EVM Interface Mapping
    4. 3.4 Power ON OFF Procedures
      1. 3.4.1 Power-On Procedure
      2. 3.4.2 Power-Off Procedure
      3. 3.4.3 Power Test Points
    5. 3.5 Peripheral and Major Component Description
      1. 3.5.1  Clocking
      2. 3.5.2  Reset
      3. 3.5.3  OLDI Display Interface
      4. 3.5.4  CSI Interface
      5. 3.5.5  Audio Codec Interface
      6. 3.5.6  HDMI Display Interface
      7. 3.5.7  JTAG Interface
      8. 3.5.8  Test Automation Header
      9. 3.5.9  UART Interface
      10. 3.5.10 USB Interface
        1. 3.5.10.1 USB 2.0 Type A Interface
        2. 3.5.10.2 USB 2.0 Type C Interface
      11. 3.5.11 Memory Interfaces
        1. 3.5.11.1 LPDDR4 Interface
        2. 3.5.11.2 OSPI Interface
        3. 3.5.11.3 MMC Interfaces
          1. 3.5.11.3.1 MMC0 - eMMC Interface
          2. 3.5.11.3.2 MMC1 - Micro SD Interface
          3. 3.5.11.3.3 MMC2 - M2 Key E Interface
        4. 3.5.11.4 EEPROM
      12. 3.5.12 Ethernet Interface
        1. 3.5.12.1 CPSW Ethernet PHY1 Default Configuration
        2. 3.5.12.2 CPSW Ethernet PHY2 Default Configuration
      13. 3.5.13 GPIO Port Expander
      14. 3.5.14 GPIO Mapping
      15. 3.5.15 Power
        1. 3.5.15.1 Power Requirements
        2. 3.5.15.2 Power Input
        3. 3.5.15.3 Power Supply
        4. 3.5.15.4 Power Sequencing
        5. 3.5.15.5 AM62x 17x17 SoC Power
        6. 3.5.15.6 Current Monitoring
      16. 3.5.16 AM62x-Low Power SK EVM User Setup and Configuration
        1. 3.5.16.1 EVM DIP Switches
        2. 3.5.16.2 Boot Modes
        3. 3.5.16.3 User Test LEDs
      17. 3.5.17 Expansion Headers
        1. 3.5.17.1 User Expansion Connector
        2. 3.5.17.2 MCU Connector
        3. 3.5.17.3 PRU Connector
      18. 3.5.18 Push Buttons
      19. 3.5.19 I2C Address Mapping
  6. 4Known Issues and Modifications
  7. 5Revision History
  8. 6IMPORTANT NOTICE AND DISCLAIMER

3.5.15.5 AM62x 17x17 SoC Power

The core voltage of the AM62x 17x17 SoC can be 0.75 V or 0.85 V based on the PMIC configuration and on the power optimization requirement. By default, the PMIC configured as VDD_CORE = 0.75V, it can be changed to 0.85V by changing the PMIC configuration register. Current monitors are provided on all the SoC power rails.

The SoC has different IO groups. Each IO group is powered by specific power supplies as shown in the table below.

Table 3-15 SoC Power Rails
Sl.NoPower SupplySoC Supply RailsIO Power GroupVoltage
1VDD_COREVDDA_CORE_USB

0.75

VDDA_CORE_CSI
VDD_CANUARTCANUART
VDD_CORECORE
2VDDR_COREVDDR_CORECORE0.85
3VDDA_1V8VDDA_1V8_CSIRX.CSI

1.8

VDDA_1V8_USBUSB
VDDA_1V8_MCU
VDDA_1V8_OLDIOLDI
VDDA_1V8_OSCOOSCO
VDDA_PLL0, VDDA_PLL1,VDDA_PLL2
4VDD_LPDDR4VDDS_DDR

DDR0

1.1

VDDS_DDR_C
5VPP_1V8VPP_1V81.8
6SoC_VDDSHV5_SDIOVDDSHV5MMC13.3
7SOC_DVDD1V8VDDSHV0General3.3
VDDSHV1OSPI1.8
VDDSHV4MMC0
VDDSHV6MMC2
VMON_1P8_SOC
8SOC_DVDD3V3VDDSHV0General

3.3

VDDSHV2RGMII
VDDSHV3GPMC
VDDSHV_MCUMCU General
VMON_3P3_SOC
VDDA_3P3_USBUSB