SPRUJ53A April 2024 – June 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
In some cases, you can simulate the CPU reset (SYSRS) in software. This can be done by setting the CPU1RSn bit to 1 in the SIMRESET register by CPU1 software. This toggles CPU1.SYSRS signals, resetting the CPU (just like the debugger reset).
After this reset, the SIMRESET_CPU1RSn bit in the RESC register is set. Software can read this bit to know the cause of the reset and clear the status by writing a 1 into the corresponding bit in the RESCCLR register.