SPRUJ53A April 2024 – June 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Memory-mapped registers in the system control operate on INTOSC1 clock domain. Any CPU writes to these registers requires a delay in between subsequent writes; otherwise, a second write can be lost. The application needs to take this into consideration and add a delay in terms of the number of NOP instructions after every write to the registers listed in Table 3-18. The formula to compute the delay between subsequent writes:
Delay (in SYSCLK cycles) = 3 × (FSYSCLK ÷ FINTOSC1) + 9
For Example: for SYSCLK = 100MHz
Delay (in SYSCLK cycles) = 3 × (100MHz ÷ 10MHz) + 9 = 39 SYSCLK cycles
Registers requiring delay after every write |
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AUXCLKDIVSEL |
CLBCLKCTL |
PERCLKDIVSEL |
SYSCLKDIVSEL |
SYSPLLCTL1 |
SYSPLLMULT |
WDCR |
XCLKOUTDIVSEL |
XTALCR |
CLKSRCCTL1 |
CLKSRCCTL2 |
CLKSRCCTL3 |
CPU1TMR2CTL |