SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Register | Value | Selected Mode |
---|---|---|
Epg1MuxRegs | ||
EPGMXSEL0.SEL0 | 0x1 | Select EPGOUT0 to drive DATAOUT[0] |
Epg1Regs | ||
Global Settings | ||
GCTL0.EPGOUT0SEL | 0x0 | Selects signal mux output on EPGOUT0 |
GCTL3.EPGOUT0_SIGOUTSEL | 0x4 | Select SIGGEN0.OUT[4] on EPGOUT0, on 64-bit reversal, 31 bit appears on 32 bit (hence, configuring to 4). |
GCTL1.SIGGEN0_CLKSEL | 0x0 | Select CLKOUT0 of CLKGEN0 as the clock source of SIGGEN0 |
CLKGEN0 Setting | ||
CLKDIV0_CTL0.PRD | 0x7 | Divide by 8 |
CLKDIV0_CLKOFFSET.CLK0OFFSET | 0x0 | No offset |
SIGGEN0 Mode and Bit Length Configuration | ||
SIGGEN0_CTL0.BITLENGTH | 0x20 | Do 32 shifts. |
SIGGEN0_CTL0.MODE | 0x1 | Configure the mode to shift right once mode. Generates an interrupt after 32 shifts. |
SIGGEN0_CTL0.BRIN | 0x1 | Reverse the bits to the data transform block to make sure that the MSB is transmitted first. |
SIGGEN0_CTL0.BROUT | 0x1 | Reverse the data back and store in the register |
SIGGEN0_DATA0[15:0] | 0xAA55 | Data to be shifted out |
SIGGEN0_DATA0[31:16] | 0xCCCC | Data to be shifted out |
SIGGEN0_DATA1[15:0] | 0xAA55 | Data to be shifted out |
SIGGEN0_DATA1[31:16] | 0x55AA | Data to be shifted out |