SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Table 5-73 lists the memory-mapped registers for the DCSM_Z1_OTP registers. All register offset addresses not listed in Table 5-73 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | Z1OTP_LINKPOINTER1 | Zone 1 Link Pointer1 | Go | |
2h | Z1OTP_LINKPOINTER2 | Zone 1 Link Pointer2 | Go | |
4h | Z1OTP_LINKPOINTER3 | Zone 1 Link Pointer3 | Go | |
6h | Z1OTP_JLM_ENABLE | Zone 1 JTAGLOCK Enable Register | Go | |
8h | Z1OTP_GPREG1 | Zone 1 General Purpose Register 1 | Go | |
Ah | Z1OTP_GPREG2 | Zone 1 General Purpose Register 2 | Go | |
Ch | Z1OTP_GPREG3 | Zone 1 General Purpose Register 3 | Go | |
Eh | Z1OTP_GPREG4 | Zone 1 General Purpose Register 4 | Go | |
10h | Z1OTP_PSWDLOCK | Secure Password Lock | Go | |
12h | Z1OTP_CRCLOCK | Secure CRC Lock | Go | |
14h | Z1OTP_JTAGPSWDH0 | JTAG Lock Permanent Password 0 | Go | |
16h | Z1OTP_JTAGPSWDH1 | JTAG Lock Permanent Password 1 | Go | |
18h | Z1OTP_CMACKEY0 | Secure Boot CMAC Key 0 | Go | |
1Ah | Z1OTP_CMACKEY1 | Secure Boot CMAC Key 1 | Go | |
1Ch | Z1OTP_CMACKEY2 | Secure Boot CMAC Key 2 | Go | |
1Eh | Z1OTP_CMACKEY3 | Secure Boot CMAC Key 3 | Go |
Complex bit access types are encoded to fit into small table cells. Table 5-74 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Reset or Default Value | ||
-n | Value after reset or the default value |
Z1OTP_LINKPOINTER1 is shown in Figure 5-66 and described in Table 5-75.
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Zone 1 Link Pointer1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_LINKPOINTER1 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_LINKPOINTER1 | R | FFFFFFFFh | Zone1 Link Pointer 1 location in USER OTP. Note: [1] ECC comparison is disabled for this location [2] When this value is loaded into DCSM, if the bits[31:14] !=0, device will remain in BLOCKED state. Before shipping parts to customers, TI would change the value of these bits to 0s. Reset type: N/A |
Z1OTP_LINKPOINTER2 is shown in Figure 5-67 and described in Table 5-76.
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Zone 1 Link Pointer2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_LINKPOINTER2 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_LINKPOINTER2 | R | FFFFFFFFh | Zone1 Link Pointer 2 location in USER OTP. Note: [1] ECC comparison is disabled for this location [2] When this value is loaded into DCSM, if the bits[31:14] !=0, device will remain in BLOCKED state. Before shipping parts to customers, TI would change the value of these bits to 0s. Reset type: N/A |
Z1OTP_LINKPOINTER3 is shown in Figure 5-68 and described in Table 5-77.
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Zone 1 Link Pointer3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_LINKPOINTER3 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_LINKPOINTER3 | R | FFFFFFFFh | Zone1 Link Pointer 3 location in USER OTP. Note: [1] ECC comparison is disabled for this location [2] When this value is loaded into DCSM, if the bits[31:14] !=0, device will remain in BLOCKED state. Before shipping parts to customers, TI would change the value of these bits to 0s. Reset type: N/A |
Z1OTP_JLM_ENABLE is shown in Figure 5-69 and described in Table 5-78.
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Zone 1 JTAGLOCK Enable Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_JLM_ENABLE | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_JLM_ENABLE | R | FFFFFFFFh | Zone1 JLM_ENABLE register location in USER OTP. Note: When this value is loaded into Z1_JLM_ENABLE, if the value is 32-bit all-1s, the JTAGLOCK will be enabled. Before shipping parts to customers, TI will program the default value to 0xFFFF_000F, which will disable the JTAGLOCK feature. Users should program 0xFFFF_0000 to enable the JTAGLOCK feature. Reset type: N/A |
Z1OTP_GPREG1 is shown in Figure 5-70 and described in Table 5-79.
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Zone 1 General Purpose Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_GPREG1 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_GPREG1 | R | FFFFFFFFh | Zone1 General Purpose register location in USER OTP. Reset type: N/A |
Z1OTP_GPREG2 is shown in Figure 5-71 and described in Table 5-80.
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Zone 1 General Purpose Register 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_GPREG2 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_GPREG2 | R | FFFFFFFFh | Zone1 General Purpose register location in USER OTP. Reset type: N/A |
Z1OTP_GPREG3 is shown in Figure 5-72 and described in Table 5-81.
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Zone 1 General Purpose Register 3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_GPREG3 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_GPREG3 | R | FFFFFFFFh | Zone1 General Purpose register location in USER OTP. Reset type: N/A |
Z1OTP_GPREG4 is shown in Figure 5-73 and described in Table 5-82.
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Zone 1 General Purpose Register 4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_GPREG4 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_GPREG4 | R | FFFFFFFFh | Zone1 General Purpose register location in USER OTP. Reset type: N/A |
Z1OTP_PSWDLOCK is shown in Figure 5-74 and described in Table 5-83.
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Secure Password Lock
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_PSWDLOCK | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_PSWDLOCK | R | FFFFFFFFh | Zone1 password lock location in USER OTP. Note: When this value is loaded into DCSM, if the value is 32-bit all-1s, CSMPSWD will remain locked. Before shipping parts to customers, TI would change the value of this location in such a way that the ECC field remains all-1s and also LSB 4-bits remain 4'b1111. Reset type: N/A |
Z1OTP_CRCLOCK is shown in Figure 5-75 and described in Table 5-84.
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Secure CRC Lock
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_CRCLOCK | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_CRCLOCK | R | FFFFFFFFh | Zone1 CRC lock location in USER OTP. Note: When this value is loaded into DCSM, if the value is 32-bit all-1s, VCU will not have ability to calculate CRC on secured memory content.. Before shipping parts to customers, TI would change the value of this location in such a way that the ECC field remains all-1s and also LSB 4-bits remain 4'b1111. Reset type: N/A |
Z1OTP_JTAGPSWDH0 is shown in Figure 5-76 and described in Table 5-85.
Return to the Summary Table.
JTAG Lock Permanent Password 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JTAGPSWDH0 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | JTAGPSWDH0 | R | FFFFFFFFh | JTAG Lock Password High 0 (bits 95:64) location in USER Z1 OTP. This value is dummy loaded into the non-memory-mapped JTAGPSWD register, bits 95:64. TI must program a default value into this location, leaving the ECC bits all 1's. Reset type: N/A |
Z1OTP_JTAGPSWDH1 is shown in Figure 5-77 and described in Table 5-86.
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JTAG Lock Permanent Password 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JTAGPSWDH1 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | JTAGPSWDH1 | R | FFFFFFFFh | JTAG Lock Password High 1 (bits 127:96) location in USER Z1 OTP. This value is dummy loaded into the non-memory-mapped JTAGPSWD register, bits 127:96. Reset type: N/A |
Z1OTP_CMACKEY0 is shown in Figure 5-78 and described in Table 5-87.
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Secure Boot CMAC Key 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMACKEY0 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CMACKEY0 | R | FFFFFFFFh | Secure Boot CMAC Key 0 (bits 31:0) location in User Z1 OTP. This value is dummy loaded into the CMACKEY0 register. Reset type: N/A |
Z1OTP_CMACKEY1 is shown in Figure 5-79 and described in Table 5-88.
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Secure Boot CMAC Key 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMACKEY1 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CMACKEY1 | R | FFFFFFFFh | Secure Boot CMAC Key 1 (bits 63:32) location in User Z1 OTP. This value is dummy loaded into the CMACKEY1 register. Reset type: N/A |
Z1OTP_CMACKEY2 is shown in Figure 5-80 and described in Table 5-89.
Return to the Summary Table.
Secure Boot CMAC Key 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMACKEY2 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CMACKEY2 | R | FFFFFFFFh | Secure Boot CMAC Key 2 (bits 95:64) location in User Z1 OTP. This value is dummy loaded into the CMACKEY2 register. Reset type: N/A |
Z1OTP_CMACKEY3 is shown in Figure 5-81 and described in Table 5-90.
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Secure Boot CMAC Key 3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMACKEY3 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CMACKEY3 | R | FFFFFFFFh | Secure Boot CMAC Key 3 (bits 127:96) location in User Z1 OTP. This value is dummy loaded into the CMACKEY3 register. Reset type: N/A |