SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Table 25-18 lists the memory-mapped registers for the FSI_TX_REGS registers. All register offset addresses not listed in Table 25-18 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Write Protection | Section |
|---|---|---|---|---|
| 0h | TX_MAIN_CTRL | Transmit main control register | EALLOW | Go |
| 2h | TX_CLK_CTRL | Transmit clock control register | EALLOW and LOCK | Go |
| 4h | TX_OPER_CTRL_LO | Transmit operation control register low | EALLOW and LOCK | Go |
| 5h | TX_OPER_CTRL_HI | Transmit operation control register high | EALLOW and LOCK | Go |
| 6h | TX_FRAME_CTRL | Transmit frame control register | Go | |
| 7h | TX_FRAME_TAG_UDATA | Transmit frame tag and user data register | Go | |
| 8h | TX_BUF_PTR_LOAD | Transmit buffer pointer control load register | EALLOW | Go |
| 9h | TX_BUF_PTR_STS | Transmit buffer pointer control status register | Go | |
| Ah | TX_PING_CTRL | Transmit ping control register | EALLOW and LOCK | Go |
| Bh | TX_PING_TAG | Transmit ping tag register | Go | |
| Ch | TX_PING_TO_REF | Transmit ping timeout counter reference | EALLOW and LOCK | Go |
| Eh | TX_PING_TO_CNT | Transmit ping timeout current count | Go | |
| 10h | TX_INT_CTRL | Transmit interrupt event control register | EALLOW and LOCK | Go |
| 11h | TX_DMA_CTRL | Transmit DMA event control register | EALLOW and LOCK | Go |
| 12h | TX_LOCK_CTRL | Transmit lock control register | EALLOW and LOCK | Go |
| 14h | TX_EVT_STS | Transmit event and error status flag register | Go | |
| 16h | TX_EVT_CLR | Transmit event and error clear register | EALLOW | Go |
| 17h | TX_EVT_FRC | Transmit event and error flag force register | EALLOW | Go |
| 18h | TX_USER_CRC | Transmit user-defined CRC register | Go | |
| 20h | TX_ECC_DATA | Transmit ECC data register | Go | |
| 22h | TX_ECC_VAL | Transmit ECC value register | Go | |
| 24h | TX_DLYLINE_CTRL | Transmit delay Line control register | EALLOW and LOCK | Go |
| 40h + formula | TX_BUF_BASE_y | Base address for transmit buffer | Go |
Complex bit access types are encoded to fit into small table cells. Table 25-19 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
| Register Array Variables | ||
| i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
| y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. | |
TX_MAIN_CTRL is shown in Figure 25-18 and described in Table 25-20.
Return to the Summary Table.
Transmit main control register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| KEY | |||||||
| W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | FLUSH | CORE_RST | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | KEY | W | 0h | Write Key In order to write to any bit in this register, 0xA5 must be written to this field at the same time. Otherwise, writes are ignored. The key is cleared immediately after writing, so it must be written again for every change to this register. Reset type: SYSRSn |
| 7-2 | RESERVED | R | 0h | Reserved |
| 1 | FLUSH | R/W | 0h | Flush Operation Start bit This bit will cause the transmitter to initiate a flush pattern of a single toggle on the TXD0 and TXD1 followed by five full cycles of TXCLK. This bit should be written only when the CORE_RST bit is 0 and the clock to the Transmitter core is turned on. 0h (R/W) = Clear this bit. 1h (R/W) = Setting this bit will Initiate flush sequence. To properly execute a flush sequence, Set FLUSH to 1, wait for five TXCLK cycles then clear FLUSH to 0. Note: The KEY field must contain 0xA5 for any write to this bit to take effect. The software must keep this bit set to 1 for at least five TXCLK cycles before setting it back to 0. Reset type: SYSRSn |
| 0 | CORE_RST | R/W | 0h | Transmitter Main Core Reset bit This bit controls the transmitter main core reset. In order to send any frame, this bit must be cleared. 0h (R/W) = Transmitter core is not in reset and can transmit frames. 1h (R/W) = Transmitter core is held in reset. Note: The KEY field must contatin 0xA5 for any write to this bit to take effect. Reset type: SYSRSn |
TX_CLK_CTRL is shown in Figure 25-19 and described in Table 25-21.
Return to the Summary Table.
Transmit clock control register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PRESCALE_VAL | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRESCALE_VAL | CLK_EN | CLK_RST | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-2 | PRESCALE_VAL | R/W | 0h | Clock Divider Prescale Value The input clock is divided by this 8-bit value and fed into the transmitter core. This divided clock is the rate at which TXCLK will operate. 0h (R/W) = Reserved 1h (R/W) = Input clock /1 2h (R/W) = Input clock /2 3h (R/W) = Input clock /3 4h (R/W) = Input clock /4 ... FFh (R/W) = Input clock /255 TXCLKIN = Input clock / PRESCALE_VAL In FSI mode: TXCLK = TXCLKIN / 2 In SPI mode: TXCLK = TXCLKIN Reset type: SYSRSn |
| 1 | CLK_EN | R/W | 0h | Clock Divider Enable bit This bit will enable and disable the input clock divider and start the clock to the transmitter core. 0h (R/W) = The input clock divider is not enabled and the clock is not connected to the transmitter core. 1h (R/W) = The input clock to the transmitter core is being divided by the PRESCALE_VAL and enabled. Reset type: SYSRSn |
| 0 | CLK_RST | R/W | 0h | Clock Divider Reset bit This bit will reset the clock counter in the clock divider. 0h (R/W) = The clock divider is set based on the value in PRESCALE_VAL. The input clock will be divided by PRESCALE_VAL if CLK_EN is set. 1h (R/W) = The clock divider will be reset to 0 and will stay reset until software writes a 0 to this bit. Reset type: SYSRSn |
TX_OPER_CTRL_LO is shown in Figure 25-20 and described in Table 25-22.
Return to the Summary Table.
Transmit operation control register low
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SEL_TDM_IN | TDM_ENABLE | SEL_PLLCLK | ||||
| R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PING_TO_MODE | SW_CRC | START_MODE | SPI_MODE | DATA_WIDTH | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-11 | RESERVED | R | 0h | Reserved |
| 10 | SEL_TDM_IN | R/W | 0h | Input TDM port Select bit This bit selects the input port for the transmitter core between the TDM input pins or the RX module. When this bit is '0', the inputs selected for TDM are from the TDM input pins. When this bit is '1', then inputs selected for TDM are from the RX module. Reset type: SYSRSn |
| 9 | TDM_ENABLE | R/W | 0h | Transmit TDM Mode Enable bit. This bit enables the TDM Mode for multi-remote TDM operation. 0h (R/W) Transmit TDM Mode is not enabled. 1h (R/W) Transmit TDM Mode is enabled. Reset type: SYSRSn |
| 8 | SEL_PLLCLK | R/W | 0h | Input Clock Select bit This bit selects the input clock source for the transmitter core. 0h (R/W) = SYSCLK is the source of the transmitter clock into the clock prescaler. 1h (R/W) = PLLRAWCLK is the source of the transmitter core clock into the clock prescaler. Reset type: SYSRSn |
| 7 | PING_TO_MODE | R/W | 0h | Ping Counter Reset Mode Select bit This bit selects when the ping counter will reset. 0h (R/W) = The ping counter will reset and restart only on hardware initiated ping frames, when ping counter has timed out. 1h (R/W) = The ping counter will reset and restart on any software initiated frame as well as a ping counter timeout Reset type: SYSRSn |
| 6 | SW_CRC | R/W | 0h | CRC Source Select bit This bit selects the source of the CRC value that is transmitted. 0h (R/W) = The transmitted CRC value is computed by hardware. 1h (R/W) = The transmitted CRC value is sourced from the value programmed in the TX_USER_CRC register. Reset type: SYSRSn |
| 5-3 | START_MODE | R/W | 0h | Transmission Start Mode Select bit These bits select the method by which a new frame transmission is started. 0h (R/W) = Only a software write to TX_FRAME_CTRL.START initiate a new transmission. 1h (R/W) = The configured external trigger will initiate a new transmission. 2h (R/W) = Either writing to TX_FRAME_CTRL.START or the TX_FRAME_TAG_UDATA register will initiate a new transmission. All other combinations of bits are illegal and reserved for future use. Reset type: SYSRSn |
| 2 | SPI_MODE | R/W | 0h | SPI Mode Select bit This bit enables and disables SPI compatibility mode. 0h (R/W) = FSI is in normal mode of operation. 1h (R/W) = FSI is operating in SPI compatibility mode. Reset type: SYSRSn |
| 1-0 | DATA_WIDTH | R/W | 0h | Transmit Data Width Select bits These bits define the number of data lines used by the transmitter. 0h (R/W) = Data will be transmitted on one data line (TXD0) 1h (R/W) = Data will be transmitted on two data lines (TXD0 and TXD1). The format of the data is described in the preceeding chapter. 2h, 3h (R/W) = Reserved Reset type: SYSRSn |
TX_OPER_CTRL_HI is shown in Figure 25-21 and described in Table 25-23.
Return to the Summary Table.
Transmit operation control register high
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | EXT_TRIG_SEL | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EXT_TRIG_SEL | ECC_SEL | FORCE_ERR | RESERVED | ||||
| R/W-0h | R/W-0h | R/W-0h | R-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-14 | RESERVED | R | 0h | Reserved |
| 13-7 | EXT_TRIG_SEL | R/W | 0h | External Trigger Select bit These bits define which of the 128 external inputs will be used as the source for the external input trigger. 00h (R/W) = Trigger 1 is the source. 01h (R/W) = Trigger 2 is the source. 02h (R/W) = Trigger 3 is the source. ... 7Fh (R/W) = Trigger 128 is the source. Reset type: SYSRSn |
| 6 | ECC_SEL | R/W | 0h | ECC Data Width Select bit This bit selects between 16-bit and 32-bit ECC computation. 0h (R/W) = 32-bit ECC is used. 1h (R/W) = 16-bit ECC is used. Reset type: SYSRSn |
| 5 | FORCE_ERR | R/W | 0h | Error Frame Force bit This bit will force the the CRC value of the transmitted data frame to 0 whenever there is a buffer overrun or underrun condition. This can be used to force a corrupted CRC as the data is not guaranteed to be reliable. The receiver will treat the data as invalid and can handle this as needed. Note: DO NOT use FORCE_ERR if using the SW CRC mode (FSI Transmit). 0h (R/W) = The CRC will not be forced to 0. 1h (R/W) = The CRC will be forced to 0 in a buffer overrun or underrun condition. Reset type: SYSRSn |
| 4-0 | RESERVED | R | 0h | Reserved |
TX_FRAME_CTRL is shown in Figure 25-22 and described in Table 25-24.
Return to the Summary Table.
Transmit frame control register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| START | RESERVED | ||||||
| R/W-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| N_WORDS | FRAME_TYPE | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | START | R/W | 0h | Start Transmission bit This bit will cause the FSI to start transmitting the next frame. 0h (R/W) = Writing a 0 to this bit will have no effect. 1h (R/W) = Start the next transmission. This bit will be cleared by hardware. Reset type: SYSRSn |
| 14-8 | RESERVED | R | 0h | Reserved |
| 7-4 | N_WORDS | R/W | 0h | Number of Words to be Transmitted This field defines the number of words which will be transmitted in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the receiver. Set this bitfield to be one less than the number of words to be transmitted. 0h (R/W) = 1 data word frame (16-bit data). 1h (R/W) = 2 data word frame (32-bit data). .. Fh (R/W) = 16 data word frame (256-bit data). Reset type: SYSRSn |
| 3-0 | FRAME_TYPE | R/W | 0h | Transmit Frame Type This field determines the type of frame that will be transmitted next. 0000b (R/W) = Ping Frame. This frame can be sent either by software or automatically by hardware. 0100b (R/W) = DATA_1_WORD Frame. One word data frame (16-bit data). 0101b (R/W) = DATA_2_WORD Frame. Two word data frame (32-bit data). 0110b (R/W) = DATA_4_WORD Frame. Four word data frame (64-bit data). 0111b (R/W) = DATA_6_WORD Frame. Six word data frame (96-bit data). 0011b (R/W) = DATA_N_WORD Frame. The N_WORDS field will determine the number of words (1 to 16) to be sent. Both the transmitter and receiver must have the same value programmed. 1111b (R/W) = Error Frame. This frame can be used during error conditions or any condition where the transmitter wants to notify the receiver of a high priorty status. However, the user software is at liberty to use this for any purpose. 0001b, 0010b, and 1000b through 1110b are Reserved and should not be used. Reset type: SYSRSn |
TX_FRAME_TAG_UDATA is shown in Figure 25-23 and described in Table 25-25.
Return to the Summary Table.
Transmit frame tag and user data register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| USER_DATA | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | FRAME_TAG | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | USER_DATA | R/W | 0h | User Data bits This is a user-defined value that will be loaded into the the user data phase of the frame. This 8-bit value can be used by the receiver for any application need. This value will not impact any hardware behavior. Reset type: SYSRSn |
| 7-4 | RESERVED | R | 0h | Reserved |
| 3-0 | FRAME_TAG | R/W | 0h | This will be used only for software initiated transmissions. Frame tag bits This is a user-defined value that will be loaded into the frame tag phase of the next transmission. The receiver may use the frame tag for any application need. This value will not impact any hardware behavior For external triggers do not use this register. Use the TX_PING_TAG register instead. Reset type: SYSRSn |
TX_BUF_PTR_LOAD is shown in Figure 25-24 and described in Table 25-26.
Return to the Summary Table.
Transmit buffer pointer control load register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BUF_PTR_LOAD | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R | 0h | Reserved |
| 3-0 | BUF_PTR_LOAD | R/W | 0h | Buffer Pointer Load bits These bits are used to force the transmit buffer pointer to a desired index within the transmit buffer. The next transmission will begin picking data from this index and increment appropriately. This value will be reflected in TX_BUF_PTR_STS only after a minimum 3 SYSCLK cycles + 3 TXCLK cycles. This value should not be written while there is an active transmission as it may corrupt the ongoing frame or other undefined behavior. Reset type: SYSRSn |
TX_BUF_PTR_STS is shown in Figure 25-25 and described in Table 25-27.
Return to the Summary Table.
Transmit buffer pointer control status register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | CURR_WORD_CNT | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CURR_BUF_PTR | ||||||
| R-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-13 | RESERVED | R | 0h | Reserved |
| 12-8 | CURR_WORD_CNT | R | 0h | Words Remaining in the transmit buffer This value indicates the number of words present in the data buffer which have not yet been transmitted. This value is only valid when there is no active transmission. Note: This value will not be valid if there is a buffer overrun or underrun condition. Reset type: SYSRSn |
| 7-4 | RESERVED | R | 0h | Reserved |
| 3-0 | CURR_BUF_PTR | R | 0h | Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission. Reset type: SYSRSn |
TX_PING_CTRL is shown in Figure 25-26 and described in Table 25-28.
Return to the Summary Table.
Transmit ping control register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | EXT_TRIG_SEL | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EXT_TRIG_SEL | EXT_TRIG_EN | TIMER_EN | CNT_RST | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-10 | RESERVED | R | 0h | Reserved |
| 9-3 | EXT_TRIG_SEL | R/W | 0h | External Trigger Select bits This bitfield will select one of the 128 external trigger inputs to as the source to generate a ping frame. A ping frame will only be generated if the EXT_TRIG_EN bit is set. 0h (R/W) = Trigger 1 will be used to generate a ping frame. 1h (R/W) = Trigger 2 will be used to generate a ping frame. .. 7Fh (R/W) = Trigger 128 will be used to generate a ping frame. Reset type: SYSRSn |
| 2 | EXT_TRIG_EN | R/W | 0h | External Trigger Enable bit This bit will allow the external trigger logic to generate a ping frame. 0h (R/W) = External triggers will not be used to generate ping frames. 1h (R/W) = The selected external trigger (selected by EXT_TRIG_SEL bits) will be able to generate a ping frame. The ping timer will be ignored if this bit is set. Reset type: SYSRSn |
| 1 | TIMER_EN | R/W | 0h | Ping Timer Enable bit This bit will enable the ping timer for generating periodic ping frames. 0h (R/W) = The ping timer is disabled and will not generate ping frames. 1h (R/W) = The ping timer is enabled and can be used to generate ping frames.Once the timer count reaches the value set by the TX_PING_TO_REF register, it will initiate a ping frame transmission. Note: If the ping timer is used, EXT_TRIG_EN should not be set as it will override this function. Reset type: SYSRSn |
| 0 | CNT_RST | R/W | 0h | Ping Counter Reset bit Writing a 1 to this bit will reset the ping counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be cleared to 0 to use the counter. 0h (R/W) = Clear the CNT_RST. 1h (R/W) = The ping counter will be reset to 0. Reset type: SYSRSn |
TX_PING_TAG is shown in Figure 25-27 and described in Table 25-29.
Return to the Summary Table.
Transmit ping tag register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TAG | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R | 0h | Reserved |
| 3-0 | TAG | R/W | 0h | Ping Frame Tag This field contains a 4-bit tag which will be sent in any ping frame that is initiated by an external trigger or the ping timer. This field is user-defined and can be set based on the application requirement. If a ping frame is generated manually, the transmitted tag will be from TX_FRAME_TAG_UDATA.FRAME_TAG, not this value. Reset type: SYSRSn |
TX_PING_TO_REF is shown in Figure 25-28 and described in Table 25-30.
Return to the Summary Table.
Transmit ping timeout counter reference
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TO_REF | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | TO_REF | R/W | 0h | Ping Timer Reference Value. This is the 32-bit reference value for the ping timer. The timer will increment the counter starting from 0. When the reference value is reached, it will generate a timeout event, triggering a ping frame transmission. The counter will then reset to 0 and continue counting. Reset type: SYSRSn |
TX_PING_TO_CNT is shown in Figure 25-29 and described in Table 25-31.
Return to the Summary Table.
Transmit ping timeout current count
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TO_CNT | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | TO_CNT | R | 0h | Ping Timer Counter Value This register contains the current value of the ping timer counter. After reset, this counter will increment until it reaches the reference value (TX_PING_TO_REF), at which point it generates a ping frame transmission. After this point, the counter will reset to 0 and continue counting. This is a free-running counter Reset type: SYSRSn |
TX_INT_CTRL is shown in Figure 25-30 and described in Table 25-32.
Return to the Summary Table.
Transmit interrupt event control register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | INT2_EN_PING_TO | INT2_EN_BUF_OVERRUN | INT2_EN_BUF_UNDERRUN | INT2_EN_FRAME_DONE | |||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | INT1_EN_PING_TO | INT1_EN_BUF_OVERRUN | INT1_EN_BUF_UNDERRUN | INT1_EN_FRAME_DONE | |||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | RESERVED | R | 0h | Reserved |
| 11 | INT2_EN_PING_TO | R/W | 0h | Enable PING Timer Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = The ping timer event will trigger an interrupt on TX_INT2. Reset type: SYSRSn |
| 10 | INT2_EN_BUF_OVERRUN | R/W | 0h | Enable Buffer Overrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Buffer Overrun condition will trigger an interrupt on TX_INT2. Reset type: SYSRSn |
| 9 | INT2_EN_BUF_UNDERRUN | R/W | 0h | Enable Buffer Underrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Buffer Underrun condition will trigger an interrupt on TX_INT2. Reset type: SYSRSn |
| 8 | INT2_EN_FRAME_DONE | R/W | 0h | Enable Frame Done interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Frame Done event will trigger an interrupt on TX_INT2. Reset type: SYSRSn |
| 7-4 | RESERVED | R | 0h | Reserved |
| 3 | INT1_EN_PING_TO | R/W | 0h | Enable Ping Timer Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = The ping timer event will trigger an interrupt on TX_INT1. Reset type: SYSRSn |
| 2 | INT1_EN_BUF_OVERRUN | R/W | 0h | Enable Buffer Overrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Buffer Overrun condition will trigger an interrupt on TX_INT1. Reset type: SYSRSn |
| 1 | INT1_EN_BUF_UNDERRUN | R/W | 0h | Enable Buffer Underrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Buffer Underrun condition will trigger an interrupt on TX_INT1. Reset type: SYSRSn |
| 0 | INT1_EN_FRAME_DONE | R/W | 0h | Enable Frame Done interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Frame Done event will trigger an interrupt on TX_INT1. Reset type: SYSRSn |
TX_DMA_CTRL is shown in Figure 25-31 and described in Table 25-33.
Return to the Summary Table.
Transmit DMA event control register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DMA_EVT_EN | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-1 | RESERVED | R | 0h | Reserved |
| 0 | DMA_EVT_EN | R/W | 0h | DMA Event Enable bit This bit will enable the DMA event to be generated upon the completion of a transmit frame. 0h (R/W) = A DMA event will not be generated. 1h (R/W) = A DMA event will be generated upon the completion of a transmitted frame. Note: The DMA event will only be generated for data frames. Reset type: SYSRSn |
TX_LOCK_CTRL is shown in Figure 25-32 and described in Table 25-34.
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Transmit lock control register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| KEY | |||||||
| W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LOCK | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | KEY | W | 0h | Write Key In order to write to this register, 0xA5 must be written to this field at the same time. Otherwise, writes are ignored. The key is cleared immediately after writing, so it must be written again for every change to this register. Reset type: SYSRSn |
| 7-1 | RESERVED | R | 0h | Reserved |
| 0 | LOCK | R/W | 0h | Control Register Lock Enable bit This bit locks the contents of all the transmit control registers that support a lock protection. Once locked, further writes will not take effect until a SYSRS has reset this register. Once set, further writes to this bit will be ignored. 0h (R/W) = Transmit control registers can be modified and are not locked. 1h (R/W) = Transmit control registers are locked and cannot be modified until this bit is cleared by SYSRS. Any further writes to this bit are ignored. Note: The KEY field must contatin 0xA5 for any write to this bit to take effect. Reset type: SYSRSn |
TX_EVT_STS is shown in Figure 25-33 and described in Table 25-35.
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Transmit event and error status flag register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PING_TRIGGERED | BUF_OVERRUN | BUF_UNDERRUN | FRAME_DONE | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R | 0h | Reserved |
| 3 | PING_TRIGGERED | R | 0h | Ping Frame Triggered Flag Bit This bit indicates that a ping frame has been triggered. This bit is set by hardware when either the ping timer or an external trigger event have occured. Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = A ping frame has not been triggered. 1h (R) = A ping frame has been triggered by either the ping timer or external trigger. To clear this bit, write to the corresponding bit in the TX_EVT_CLR register. Reset type: SYSRSn |
| 2 | BUF_OVERRUN | R | 0h | Buffer Overrun Flag Bit This bit inditcates that buffer overrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Buffer Overrun has not occured. 1h (R) = Buffer Overrun has occured. To clear this bit, write to the corresponding bit in the TX_EVT_CLR register. Reset type: SYSRSn |
| 1 | BUF_UNDERRUN | R | 0h | Buffer Underrun Flag Bit This bit inditcates that buffer underrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Buffer Underrun has not occured. 1h (R) = Buffer Underrun has occured. To clear this bit, write to the corresponding bit in the TX_EVT_CLR register. Reset type: SYSRSn |
| 0 | FRAME_DONE | R | 0h | Frame Done Flag Bit This bit inditcates a Frame Done condition. This bit is set by hardware when a frame transmission has been completed. Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Frame Done condition has not occured. 1h (R) = Frame Done condition has occured. To clear this bit, write to the corresponding bit in the TX_EVT_CLR register. Reset type: SYSRSn |
TX_EVT_CLR is shown in Figure 25-34 and described in Table 25-36.
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Transmit event and error clear register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PING_TRIGGERED | BUF_OVERRUN | BUF_UNDERRUN | FRAME_DONE | |||
| R-0h | W-0h | W-0h | W-0h | W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R | 0h | Reserved |
| 3 | PING_TRIGGERED | W | 0h | Ping Frame Triggered Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0. Note: This bit may not always be cleared when writing to the corresponding TX_EVT_CLR bit. If PING_TIMEOUT MODE is configured to be 0, a hardware ping timeout may occur when another frame is actively being transmitted. In this case, if this bit still shows as 1 after the clear bit is written then the ping frame has been triggered but not serviced. This bit does not indicate that the ping frame has been completely sent, only that it has been triggered by the timeout event. Reset type: SYSRSn |
| 2 | BUF_OVERRUN | W | 0h | Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0. Reset type: SYSRSn |
| 1 | BUF_UNDERRUN | W | 0h | Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0. Reset type: SYSRSn |
| 0 | FRAME_DONE | W | 0h | Frame Done Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0. Reset type: SYSRSn |
TX_EVT_FRC is shown in Figure 25-35 and described in Table 25-37.
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Transmit event and error flag force register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PING_TRIGGERED | BUF_OVERRUN | BUF_UNDERRUN | FRAME_DONE | |||
| R-0h | W-0h | W-0h | W-0h | W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | RESERVED | R | 0h | Reserved |
| 3 | PING_TRIGGERED | W | 0h | Ping Frame Triggered Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Force the corresponding flag bit in the TX_EVT_STS Register. Reset type: SYSRSn |
| 2 | BUF_OVERRUN | W | 0h | Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (R/W) = Writing a 0 to this bit will have no effect. 1h (R/W) = Force the corresponding flag bit in the TX_EVT_STS Register. Reset type: SYSRSn |
| 1 | BUF_UNDERRUN | W | 0h | Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Force the corresponding flag bit in the TX_EVT_STS Register. Reset type: SYSRSn |
| 0 | FRAME_DONE | W | 0h | Frame Done Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Force the corresponding flag bit in the TX_EVT_STS Register. Reset type: SYSRSn |
TX_USER_CRC is shown in Figure 25-36 and described in Table 25-38.
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Transmit user-defined CRC register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| USER_CRC | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-8 | RESERVED | R | 0h | Reserved |
| 7-0 | USER_CRC | R/W | 0h | User-defined CRC This register contains the 8-bit CRC value to be transmitted in the next frame if the transmission is set for user-defined CRC option (TX_OPER_CTRL_LO.SW_CRC = 1). This register is ignored if the hardware CRC generation is enabled. Reset type: SYSRSn |
TX_ECC_DATA is shown in Figure 25-37 and described in Table 25-39.
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Transmit ECC data register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA_HIGH | DATA_LOW | ||||||||||||||||||||||||||||||
| R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | DATA_HIGH | R/W | 0h | Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a 32-bit write when needing to compute ECC for 32-bits for the full TX_ECC_DATA register. Reset type: SYSRSn |
| 15-0 | DATA_LOW | R/W | 0h | Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when needing to compute ECC for 16-bits. Reset type: SYSRSn |
TX_ECC_VAL is shown in Figure 25-38 and described in Table 25-40.
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Transmit ECC value register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ECC_VAL | ||||||
| R-0h | R-Ch | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-7 | RESERVED | R | 0h | Reserved |
| 6-0 | ECC_VAL | R | Ch | Computed ECC Value This field contains the ECC value computed using SEC-DED either for 16-bit or 32-bit data in the TX_ECC_DATA register. Reset type: SYSRSn |
TX_DLYLINE_CTRL is shown in Figure 25-39 and described in Table 25-41.
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Transmit delay Line control register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | TXD1_DLY | TXD0_DLY | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TXD0_DLY | TXCLK_DLY | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | Reserved |
| 14-10 | TXD1_DLY | R/W | 0h | Delay Line Tap Select for TXD1 This bitfield selects the number of delay elements inserted into the TXD1 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXD1 path. TXD1 is taken directly from the pin. 1h (R/W) One delay element is included in the TXD1 path. 2h (R/W) Two delay elements are included in the TXD1 path. ... 1Fh (R/W) 31 delay elements are included in the TXD1 path, the maximum. Reset type: SYSRSn |
| 9-5 | TXD0_DLY | R/W | 0h | Delay Line Tap Select for TXD0 This bitfield selects the number of delay elements inserted into the TXD0 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXD0 path. TXD0 is taken directly from the pin. 1h (R/W) One delay element is included in the TXD0 path. 2h (R/W) Two delay elements are included in the TXD0 path. ... 1Fh (R/W) 31 delay elements are included in the TXD0 path, the maximum. Reset type: SYSRSn |
| 4-0 | TXCLK_DLY | R/W | 0h | Delay Line Tap Select for TXCLK This bitfield selects the number of delay elements inserted into the TXCLK path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXCLK path. TXCLK is taken directly from the pin. 1h (R/W) One delay element is included in the TXCLK path. 2h (R/W) Two delay elements are included in the TXCLK path. ... 1Fh (R/W) 31 delay elements are included in the TXCLK path, the maximum. Reset type: SYSRSn |
TX_BUF_BASE_y is shown in Figure 25-40 and described in Table 25-42.
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Base address for transmit buffer
Offset = 40h + (y * 1h); where y = 0h to Fh
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| BASE_ADDRESS | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BASE_ADDRESS | |||||||
| R/W-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | BASE_ADDRESS | R/W | 0h | Transmit Data Buffer Base Address This is the base address of the 16-word data buffer used by the transmitter. Reset type: SYSRSn |