SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Table 26-9 lists the memory-mapped registers for the I2C_REGS registers. All register offset addresses not listed in Table 26-9 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | I2COAR | I2C Own address | Go | |
1h | I2CIER | I2C Interrupt Enable | Go | |
2h | I2CSTR | I2C Status | Go | |
3h | I2CCLKL | I2C Clock low-time divider | Go | |
4h | I2CCLKH | I2C Clock high-time divider | Go | |
5h | I2CCNT | I2C Data count | Go | |
6h | I2CDRR | I2C Data receive | Go | |
7h | I2CTAR | I2C TARGET address | Go | |
8h | I2CDXR | I2C Data Transmit | Go | |
9h | I2CMDR | I2C Mode | Go | |
Ah | I2CISRC | I2C Interrupt Source | Go | |
Bh | I2CEMDR | I2C Extended Mode | Go | |
Ch | I2CPSC | I2C Prescaler | Go | |
20h | I2CFFTX | I2C FIFO Transmit | Go | |
21h | I2CFFRX | I2C FIFO Receive | Go |
Complex bit access types are encoded to fit into small table cells. Table 26-10 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1C | W 1C | Write 1 to clear |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
I2COAR is shown in Figure 26-21 and described in Table 26-11.
Return to the Summary Table.
The I2C own address register (I2COAR) is a 16-bit register. The I2C module uses this register to specify its own TARGET address, which distinguishes it from other TARGETs connected to the I2C-bus. If the 7-bit addressing mode is selected (XA = 0 in I2CMDR), only bits 6-0 are used
write 0s to bits 9-7.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | OAR | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OAR | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R | 0h | Reserved |
9-0 | OAR | R/W | 0h | In 7-bit addressing mode (XA = 0 in I2CMDR): 00h-7Fh Bits 6-0 provide the 7-bit TARGET address of the I2C module. Write 0s to bits 9-7. In 10-bit addressing mode (XA = 1 in I2CMDR): 000h-3FFh Bits 9-0 provide the 10-bit TARGET address of the I2C module. Reset type: SYSRSn |
I2CIER is shown in Figure 26-22 and described in Table 26-12.
Return to the Summary Table.
I2CIER is used by the CPU to individually enable or disable I2C interrupt requests.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SCL_ECS | RESERVED | ||||||
R/W-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AAT | SCD | XRDY | RRDY | ARDY | NACK | ARBL |
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SCL_ECS | R/W | 0h | SCL Extended Automatic Clock Stretch interrupt enable Reset type: SYSRSn 0h (R/W) = Interrupt request disabled 1h (R/W) = Interrupt request enabled |
14-7 | RESERVED | R | 0h | Reserved |
6 | AAT | R/W | 0h | Addressed as TARGET interrupt enable Reset type: SYSRSn 0h (R/W) = Interrupt request disabled 1h (R/W) = Interrupt request enabled |
5 | SCD | R/W | 0h | Stop condition detected interrupt enable Reset type: SYSRSn 0h (R/W) = Interrupt request disabled 1h (R/W) = Interrupt request enabled |
4 | XRDY | R/W | 0h | Transmit-data-ready interrupt enable bit. This bit should not be set when using FIFO mode. Reset type: SYSRSn 0h (R/W) = Interrupt request disabled 1h (R/W) = Interrupt request enabled |
3 | RRDY | R/W | 0h | Receive-data-ready interrupt enable bit. This bit should not be set when using FIFO mode. Reset type: SYSRSn 0h (R/W) = Interrupt request disabled 1h (R/W) = Interrupt request enabled |
2 | ARDY | R/W | 0h | Register-access-ready interrupt enable Reset type: SYSRSn 0h (R/W) = Interrupt request disabled 1h (R/W) = Interrupt request enabled |
1 | NACK | R/W | 0h | No-acknowledgment interrupt enable Reset type: SYSRSn 0h (R/W) = Interrupt request disabled 1h (R/W) = Interrupt request enabled |
0 | ARBL | R/W | 0h | Arbitration-lost interrupt enable Reset type: SYSRSn 0h (R/W) = Interrupt request disabled 1h (R/W) = Interrupt request enabled |
I2CSTR is shown in Figure 26-23 and described in Table 26-13.
Return to the Summary Table.
The I2C status register (I2CSTR) is a 16-bit register used to determine which interrupt has occurred and to read status information.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SCL_ECS | TDIR | NACKSNT | BB | RSFULL | XSMT | AAT | AD0 |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R-0h | R-0h | R-1h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BYTESENT | SCD | XRDY | RRDY | ARDY | NACK | ARBL |
R-0h | R/W1C-0h | R/W1C-0h | R-1h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | SCL_ECS | R/W1C | 0h | SCL Status bit in extended automatic clock stretching mode 0: SCL line is pulled high. 1: SCL line is pulled low after ACK (or) NACK phase. Writing '1' to this bit releases SCL. SCL line is pulled high. Note: This bit is applicable only for extended clock stretching mode Reset type: SYSRSn 0h (R/W) = SCL line is not pulled low in extended automatic clock stretching mode. SCL_ECS bit is cleared by one o fthe following events: - It is manually cleared. To clear this bit, write a 1 to it. - The I2C module is reset. 1h (R/W) = SCL line is pulled low in extended automatic clock stretching mode. |
14 | TDIR | R/W1C | 0h | TARGET direction bit Reset type: SYSRSn 0h (R/W) = I2C is not addressed as a TARGET transmitter. TDIR is cleared by one of the following events: - It is manually cleared. To clear this bit, write a 1 to it. - Digital loopback mode is enabled. - A START or STOP condition occurs on the I2C bus. 1h (R/W) = I2C is addressed as a TARGET transmitter. |
13 | NACKSNT | R/W1C | 0h | NACK sent bit. This bit is used when the I2C module is in the receiver mode. One instance in which NACKSNT is affected is when the NACK mode is used (see the description for NACKMOD in Reset type: SYSRSn 0h (R/W) = NACK not sent. NACKSNT bit is cleared by any one of the following events: - It is manually cleared. To clear this bit, write a 1 to it. - The I2C module is reset (either when 0 is written to the IRS bit of I2CMDR or when the whole device is reset). 1h (R/W) = NACK sent: A no-acknowledge bit was sent during the acknowledge cycle on the I2C-bus. |
12 | BB | R | 0h | Bus busy bit. BB indicates whether the I2C-bus is busy or is free for another data transfer. See the paragraph following the table for more information Reset type: SYSRSn 0h (R/W) = Bus free. BB is cleared by any one of the following events: - The I2C module receives or transmits a STOP bit (bus free). - The I2C module is reset. 1h (R/W) = Bus busy: The I2C module has received or transmitted a START bit on the bus. |
11 | RSFULL | R | 0h | Receive shift register full bit. RSFULL indicates an overrun condition during reception. Overrun occurs when new data is received into the shift register (I2CRSR) and the old data has not been read from the receive register (I2CDRR). As new bits arrive from the SDA pin, they overwrite the bits in I2CRSR. The new data will not be copied to ICDRR until the previous data is read. Reset type: SYSRSn 0h (R/W) = No overrun detected. RSFULL is cleared by any one of the following events: - I2CDRR is read by the CPU. Emulator reads of the I2CDRR do not affect this bit. - The I2C module is reset. 1h (R/W) = Overrun detected |
10 | XSMT | R | 1h | Transmit shift register empty bit. XSMT = 0 indicates that the transmitter has experienced underflow. Underflow occurs when the transmit shift register (I2CXSR) is empty but the data transmit register (I2CDXR) has not been loaded since the last I2CDXR-to-I2CXSR transfer. The next I2CDXR-to-I2CXSR transfer will not occur until new data is in I2CDXR. If new data is not transferred in time, the previous data may be re-transmitted on the SDA pin. Reset type: SYSRSn 0h (R/W) = Underflow detected (empty) 1h (R/W) = No underflow detected (not empty). XSMT is set by one of the following events: - Data is written to I2CDXR. - The I2C module is reset |
9 | AAT | R | 0h | Addressed-as-TARGET bit Reset type: SYSRSn 0h (R/W) = In the 7-bit addressing mode, the AAT bit is cleared when receiving a NACK, a STOP condition, or a repeated START condition. In the 10-bit addressing mode, the AAT bit is cleared when receiving a NACK, a STOP condition, or by a TARGET address different from the I2C peripheral's own TARGET address. 1h (R/W) = The I2C module has recognized its own TARGET address or an address of all zeros (general call). |
8 | AD0 | R | 0h | Address 0 bits Reset type: SYSRSn 0h (R/W) = AD0 has been cleared by a START or STOP condition. 1h (R/W) = An address of all zeros (general call) is detected. |
7 | RESERVED | R | 0h | Reserved |
6 | BYTESENT | R/W1C | 0h | Byte Transmit over indication. BYTESENT is set when the CONTROLLER/TARGET has successfully sent the byte on SCL/SDA lines. This is diagnostic register which needs to be explicitly cleared by Software. In case not cleared the stale status would keep reflecting as no automated clear incorporated to avoid corner conditions. Reset type: SYSRSn 0h (R/W) = The I2C module has not finished transmitting the next data byte. BYTESENT is cleared by any one of the following events: - It is manually cleared. To clear this bit, write a 1 to it. - The I2C module is reset. 1h (R/W) = The I2C module has completed the transmission of a byte. |
5 | SCD | R/W1C | 0h | Stop condition detected bit. SCD is set when the I2C sends or receives a STOP condition. The I2C module delays clearing of the I2CMDR[STP] bit until the SCD bit is set. Reset type: SYSRSn 0h (R/W) = STOP condition not detected since SCD was last cleared. SCD is cleared by any one of the following events: - I2CISRC is read by the CPU when it contains the value 110b (stop condition detected). Emulator reads of the I2CISRC do not affect this bit. - SCD is manually cleared. To clear this bit, write a 1 to it. - The I2C module is reset. 1h (R/W) = A STOP condition has been detected on the I2C bus. |
4 | XRDY | R | 1h | Transmit-data-ready interrupt flag bit. When not in FIFO mode, XRDY indicates that the data transmit register (I2CDXR) is ready to accept new data. FCM=0 : When the previous data has been copied from I2CDXR to the transmit shift register (I2CXSR). The CPU can poll XRDY or use the XRDY interrupt request When in FIFO mode, use TXFFINT instead. FCM=1: XRDY is asserted only when next data is required it gets deasserted with write to I2CDXR. Both Polling and interrupt based data transfers are allowed in the FCM mode. Reset type: SYSRSn 0h (R/W) = I2CDXR not ready. XRDY is cleared when data is written to I2CDXR. 1h (R/W) = I2CDXR ready: Data has been copied from I2CDXR to I2CXSR. XRDY is also forced to 1 when the I2C module is reset. |
3 | RRDY | R/W1C | 0h | Receive-data-ready interrupt flag bit. When not in FIFO mode, RRDY indicates that the data receive register (I2CDRR) is ready to be read because data has been copied from the receive shift register (I2CRSR) to I2CDRR. The CPU can poll RRDY or use the RRDY interrupt request When in FIFO mode, use RXFFINT instead. Reset type: SYSRSn 0h (R/W) = I2CDRR not ready. RRDY is cleared by any one of the following events: - I2CDRR is read by the CPU. Emulator reads of the I2CDRR do not affect this bit. - RRDY is manually cleared. To clear this bit, write a 1 to it. - The I2C module is reset. 1h (R/W) = I2CDRR ready: Data has been copied from I2CRSR to I2CDRR. |
2 | ARDY | R/W1C | 0h | Register-access-ready interrupt flag bit (only Applicable when the I2C module is in the CONTROLLER mode). ARDY indicates that the I2C module registers are ready to be accessed because the previously programmed address, data, and command values have been used. The CPU can poll ARDY or use the ARDY interrupt request Reset type: SYSRSn 0h (R/W) = The registers are not ready to be accessed. ARDY is cleared by any one of the following events: - The I2C module starts using the current register contents. - ARDY is manually cleared. To clear this bit, write a 1 to it. - The I2C module is reset. 1h (R/W) = The registers are ready to be accessed. In the nonrepeat mode (RM = 0 in I2CMDR): If STP = 0 in I2CMDR, the ARDY bit is set when the internal data counter counts down to 0. If STP = 1, ARDY is not affected (instead, the I2C module generates a STOP condition when the counter reaches 0). In the repeat mode (RM = 1): ARDY is set at the end of each byte transmitted from I2CDXR. |
1 | NACK | R/W1C | 0h | No-acknowledgment interrupt flag bit. NACK applies when the I2C module is a CONTROLLER transmitter (or) TARGET transmitter. NACK indicates whether the I2C module has detected an acknowledge bit (ACK) or a noacknowledge bit (NACK). The CPU can poll NACK or use the NACK interrupt request. Reset type: SYSRSn 0h (R/W) = ACK received/NACK not received. This bit is cleared by any one of the following events: - An acknowledge bit (ACK) has been sent by the TARGET receiver. - NACK is manually cleared. To clear this bit, write a 1 to it. - The CPU reads the interrupt source register (I2CISRC) and the register contains the code for a NACK interrupt. Emulator reads of the I2CISRC do not affect this bit. - The I2C module is reset. 1h (R/W) = NACK bit received. The hardware detects that a no-acknowledge (NACK) bit has been received. Note: While the I2C module performs a general call transfer, NACK is 1, even if one or more TARGETs send acknowledgment. |
0 | ARBL | R/W1C | 0h | Arbitration-lost interrupt flag bit (only applicable when the I2C module is a CONTROLLER-transmitter). ARBL primarily indicates when the I2C module has lost an arbitration contest with another CONTROLLERtransmitter. The CPU can poll ARBL or use the ARBL interrupt request. Reset type: SYSRSn 0h (R/W) = Arbitration not lost. AL is cleared by any one of the following events: - AL is manually cleared. To clear this bit, write a 1 to it. - The CPU reads the interrupt source register (I2CISRC) and the register contains the code for an AL interrupt. Emulator reads of the I2CISRC do not affect this bit. - The I2C module is reset. 1h (R/W) = Arbitration lost. AL is set by any one of the following events: - The I2C module senses that it has lost an arbitration with two or more competing transmitters that started a transmission almost simultaneously. - The I2C module attempts to start a transfer while the BB (bus busy) bit is set to 1. When AL becomes 1, the CNT and STP bits of I2CMDR are cleared, and the I2C module becomes a TARGET-receiver. |
I2CCLKL is shown in Figure 26-24 and described in Table 26-14.
Return to the Summary Table.
I2C Clock low-time divider
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
I2CCLKL | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I2CCLKL | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | I2CCLKL | R/W | 0h | Clock low-time divide-down value. To produce the low time duration of the CONTROLLER clock, the period of the module clock is multiplied by (ICCL + d). d is an adjustment factor based on the prescaler. See the Clock Divider Registers section of the Introduction for details. Note: These bits must be set to a non-zero value for proper I2C clock generation. Reset type: SYSRSn |
I2CCLKH is shown in Figure 26-25 and described in Table 26-15.
Return to the Summary Table.
I2C Clock high-time divider
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
I2CCLKH | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I2CCLKH | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | I2CCLKH | R/W | 0h | Clock high-time divide-down value. To produce the high time duration of the CONTROLLER clock, the period of the module clock is multiplied by (ICCL + d). d is an adjustment factor based on the prescaler. See the Clock Divider Registers section of the Introduction for details. Note: These bits must be set to a non-zero value for proper I2C clock generation. Reset type: SYSRSn |
I2CCNT is shown in Figure 26-26 and described in Table 26-16.
Return to the Summary Table.
I2CCNT is a 16-bit register used to indicate how many data bytes to transfer when the I2C module is configured as a transmitter, or to receive when configured as a CONTROLLER receiver. In the repeat mode (RM = 1), I2CCNT is not used.
The value written to I2CCNT is copied to an internal data counter. The internal data counter is decremented by 1 for each byte transferred (I2CCNT remains unchanged). If a STOP condition is requested in the CONTROLLER mode (STP = 1 in I2CMDR), the I2C module terminates the transfer with a STOP condition when the countdown is complete (that is, when the last byte has been transferred).
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
I2CCNT | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I2CCNT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | I2CCNT | R/W | 0h | Data count value. I2CCNT indicates the number of data bytes to transfer or receive. If a STOP condition is specified (STP=1) then I2CCNT will decrease after each byte is sent until it reaches zero, which in turn will generate a STOP condition. The value in I2CCNT is a don't care when the RM bit in I2CMDR is set to 1. Reset type: SYSRSn 0h (R/W) = data count value is 65536 1h (R/W) = data count value is 1 2h (R/W) = data count value is 2 FFFFh (R/W) = data count value is 65535 |
I2CDRR is shown in Figure 26-27 and described in Table 26-17.
Return to the Summary Table.
I2CDRR is a 16-bit register used by the CPU to read received data. The I2C module can receive a data byte with 1 to 8 bits. The number of bits is selected with the bit count (BC) bits in I2CMDR. One bit at a time is shifted in from the SDA pin to the receive shift register (I2CRSR). When a complete data byte has been received, the I2C module copies the data byte from I2CRSR to I2CDRR. The CPU cannot access I2CRSR directly.
If a data byte with fewer than 8 bits is in I2CDRR, the data value is right-justified, and the other bits of I2CDRR(7-0) are undefined. For example, if BC = 011 (3-bit data size), the receive data is in I2CDRR(2-0), and the content of I2CDRR(7-3) is undefined.
When in the receive FIFO mode, the I2CDRR register acts as the receive FIFO buffer.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0h | Reserved |
7-0 | DATA | R | 0h | Receive data Reset type: SYSRSn |
I2CTAR is shown in Figure 26-28 and described in Table 26-18.
Return to the Summary Table.
The I2C TARGET address register (I2CSAR) is a 16-bit register for storing the next TARGET address that will be transmitted by the I2C module when it is a CONTROLLER. The SAR field of I2CSAR contains a 7-bit or 10-bit TARGET address. When the I2C module is not using the free data format (FDF = 0 in I2CMDR), it uses this address to initiate data transfers with a TARGET, or TARGETs. When the address is nonzero, the address is for a particular TARGET. When the address is 0, the address is a general call to all TARGETs. If the 7-bit addressing mode is selected (XA = 0 in I2CMDR), only bits 6-0 of I2CSAR are used
write 0s to bits 9-7.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TAR | ||||||
R-0h | R/W-3FFh | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TAR | |||||||
R/W-3FFh | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R | 0h | Reserved |
9-0 | TAR | R/W | 3FFh | In 7-bit addressing mode (XA = 0 in I2CMDR): 00h-7Fh Bits 6-0 provide the 7-bit TARGET address that the I2C module transmits when it is in the CONTROLLER-transmitter mode. Write 0s to bits 9-7. In 10-bit addressing mode (XA = 1 in I2CMDR): 000h-3FFh Bits 9-0 provide the 10-bit TARGET address that the I2C module transmits when it is in the CONTROLLER transmitter mode. Reset type: SYSRSn |
I2CDXR is shown in Figure 26-29 and described in Table 26-19.
Return to the Summary Table.
The CPU writes transmit data to I2CDXR. This 16-bit register accepts a data byte with 1 to 8 bits. Before writing to I2CDXR, specify how many bits are in a data byte by loading the appropriate value into the bit count (BC) bits of I2CMDR. When writing a data byte with fewer than 8 bits, make sure the value is right-aligned in I2CDXR.
After a data byte is written to I2CDXR, the I2C module copies the data byte to the transmit shift register (I2CXSR). The CPU cannot access I2CXSR directly. From I2CXSR, the I2C module shifts the data byte out on the SDA pin, one bit at a time.
When in the transmit FIFO mode, the I2CDXR register acts as the transmit FIFO buffer.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0h | Reserved |
7-0 | DATA | R/W | 0h | Transmit data Reset type: SYSRSn |
I2CMDR is shown in Figure 26-30 and described in Table 26-20.
Return to the Summary Table.
The I2C mode register (I2CMDR) is a 16-bit register that contains the control bits of the I2C module.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NACKMOD | FREE | STT | RESERVED | STP | CNT | TRX | XA |
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RM | DLB | IRS | STB | FDF | BC | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | NACKMOD | R/W | 0h | NACK mode bit. This bit is only applicable when the I2C module is acting as a receiver. Reset type: SYSRSn 0h (R/W) = In the TARGET-receiver mode: The I2C module sends an acknowledge (ACK) bit to the transmitter during each acknowledge cycle on the bus. The I2C module only sends a no-acknowledge (NACK) bit if you set the NACKMOD bit. In the CONTROLLER-receiver mode: The I2C module sends an ACK bit during each acknowledge cycle until the internal data counter counts down to 0. At that point, the I2C module sends a NACK bit to the transmitter. To have a NACK bit sent earlier, you must set the NACKMOD bit 1h (R/W) = In either TARGET-receiver or CONTROLLER-receiver mode: The I2C module sends a NACK bit to the transmitter during the next acknowledge cycle on the bus. Once the NACK bit has been sent, NACKMOD is cleared. Important: To send a NACK bit in the next acknowledge cycle, you must set NACKMOD before the rising edge of the last data bit. |
14 | FREE | R/W | 0h | This bit controls the action taken by the I2C module when a debugger breakpoint is encountered. Reset type: SYSRSn 0h (R/W) = When I2C module is CONTROLLER: If SCL is low when the breakpoint occurs, the I2C module stops immediately and keeps driving SCL low, whether the I2C module is the transmitter or the receiver. If SCL is high, the I2C module waits until SCL becomes low and then stops. When I2C module is TARGET: A breakpoint forces the I2C module to stop when the current transmission/reception is complete. 1h (R/W) = The I2C module runs free that is, it continues to operate when a breakpoint occurs. |
13 | STT | R/W | 0h | START condition bit (only applicable when the I2C module is a CONTROLLER). The RM, STT, and STP bits determine when the I2C module starts and stops data transmissions (see Table 9-6). Note that the STT and STP bits can be used to terminate the repeat mode, and that this bit is not writable when IRS = 0. Reset type: SYSRSn 0h (R/W) = In the CONTROLLER mode, STT is automatically cleared after the START condition has been generated. 1h (R/W) = In the CONTROLLER mode, setting STT to 1 causes the I2C module to generate a START condition on the I2C-bus |
12 | RESERVED | R | 0h | Reserved |
11 | STP | R/W | 0h | STOP condition bit (only applicable when the I2C module is a CONTROLLER). In the CONTROLLER mode, the RM,STT, and STP bits determine when the I2C module starts and stops data transmissions. Note that the STT and STP bits can be used to terminate the repeat mode, and that this bit is not writable when IRS=0. When in non-repeat mode, at least one byte must be transferred before a stop condition can be generated. The I2C module delays clearing of this bit until after the I2CSTR[SCD] bit is set. To avoid disrupting the I2C state machine, the user must wait until this bit is clear before initiating a new message. Reset type: SYSRSn 0h (R/W) = STP is automatically cleared after the STOP condition has been generated 1h (R/W) = STP has been set by the device to generate a STOP condition when the internal data counter of the I2C module counts down to 0. |
10 | CNT | R/W | 0h | CONTROLLER mode bit. CNT determines whether the I2C module is in the TARGET mode or the CONTROLLER mode. CNT is automatically changed from 1 to 0 when the I2C CONTROLLER generates a STOP condition Reset type: SYSRSn 0h (R/W) = TARGET mode. The I2C module is a TARGET and receives the serial clock from the CONTROLLER. 1h (R/W) = CONTROLLER mode. The I2C module is a CONTROLLER and generates the serial clock on the SCL pin. |
9 | TRX | R/W | 0h | Transmitter mode bit. When relevant, TRX selects whether the I2C module is in the transmitter mode or the receiver mode. Reset type: SYSRSn 0h (R/W) = Receiver mode. The I2C module is a receiver and receives data on the SDA pin. 1h (R/W) = Transmitter mode. The I2C module is a transmitter and transmits data on the SDA pin. |
8 | XA | R/W | 0h | Expanded address enable bit. Reset type: SYSRSn 0h (R/W) = 7-bit addressing mode (normal address mode). The I2C module transmits 7-bit TARGET addresses (from bits 6-0 of I2CTAR), and its own TARGET address has 7 bits (bits 6-0 of I2COAR). 1h (R/W) = 10-bit addressing mode (expanded address mode). The I2C module transmits 10-bit TARGET addresses (from bits 9-0 of I2CTAR), and its own TARGET address has 10 bits (bits 9-0 of I2COAR). |
7 | RM | R/W | 0h | Repeat mode bit (only applicable when the I2C module is a CONTROLLER-transmitter or CONTROLLER-receiver). The RM, STT, and STP bits determine when the I2C module starts and stops data transmissions Reset type: SYSRSn 0h (R/W) = Nonrepeat mode. The value in the data count register (I2CCNT) determines how many bytes are received/transmitted by the I2C module. 1h (R/W) = Repeat mode. A data byte is transmitted each time the I2CDXR register is written to (or until the transmit FIFO is empty when in FIFO mode) until the STP bit is manually set. The value of I2CCNT is ignored. The ARDY bit/interrupt can be used to determine when the I2CDXR (or FIFO) is ready for more data, or when the data has all been sent and the CPU is allowed to write to the STP bit. |
6 | DLB | R/W | 0h | Digital loopback mode bit. Reset type: SYSRSn 0h (R/W) = Digital loopback mode is disabled. 1h (R/W) = Digital loopback mode is enabled. For proper operation in this mode, the CNT bit must be 1. In the digital loopback mode, data transmitted out of I2CDXR is received in I2CDRR after n device cycles by an internal path, where: n = ((I2C input clock frequency/module clock frequency) x 8) The transmit clock is also the receive clock. The address transmitted on the SDA pin is the address in I2COAR. Note: The free data format (FDF = 1) is not supported in the digital loopback mode. |
5 | IRS | R/W | 0h | I2C module reset bit. Reset type: SYSRSn 0h (R/W) = The I2C module is in reset/disabled. When this bit is cleared to 0, all status bits (in I2CSTR) are set to their default values. 1h (R/W) = The I2C module is enabled. This has the effect of releasing the I2C bus if the I2C peripheral is holding it. |
4 | STB | R/W | 0h | START byte mode bit. This bit is only applicable when the I2C module is a CONTROLLER. As described in version 2.1 of the Philips Semiconductors I2C-bus specification, the START byte can be used to help a TARGET that needs extra time to detect a START condition. When the I2C module is a TARGET, it ignores a START byte from a CONTROLLER, regardless of the value of the STB bit. Reset type: SYSRSn 0h (R/W) = The I2C module is not in the START byte mode. 1h (R/W) = The I2C module is in the START byte mode. When you set the START condition bit (STT), the I2C module begins the transfer with more than just a START condition. Specifically, it generates: 1. A START condition 2. A START byte (0000 0001b) 3. A dummy acknowledge clock pulse 4. A repeated START condition Then, as normal, the I2C module sends the TARGET address that is in I2CTAR. |
3 | FDF | R/W | 0h | Free data format mode bit. Reset type: SYSRSn 0h (R/W) = Free data format mode is disabled. Transfers use the 7-/10-bit addressing format selected by the XA bit. 1h (R/W) = Free data format mode is enabled. Transfers have the free data (no address) format described in Section 9.2.5. The free data format is not supported in the digital loopback mode (DLB=1). |
2-0 | BC | R/W | 0h | Bit count bits. BC defines the number of bits (1 to 8) in the next data byte that is to be received or transmitted by the I2C module. The number of bits selected with BC must match the data size of the other device. Notice that when BC = 000b, a data byte has 8 bits. BC does not affect address bytes, which always have 8 bits. Note: If the bit count is less than 8, receive data is right-justified in I2CDRR(7-0), and the other bits of I2CDRR(7-0) are undefined. Also, transmit data written to I2CDXR must be right-justified Reset type: SYSRSn 0h (R/W) = 8 bits per data byte 1h (R/W) = 1 bit per data byte 2h (R/W) = 2 bits per data byte 3h (R/W) = 3 bits per data byte 4h (R/W) = 4 bits per data byte 5h (R/W) = 5 bits per data byte 6h (R/W) = 6 bits per data byte 7h (R/W) = 7 bits per data byte |
I2CISRC is shown in Figure 26-31 and described in Table 26-21.
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The I2C interrupt source register (I2CISRC) is a 16-bit register used by the CPU to determine which event generated the I2C interrupt.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WRITE_ZEROS | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTCODE | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11-8 | WRITE_ZEROS | R/W | 0h | TI internal testing bits These reserved bit locations should always be written as zeros. Reset type: SYSRSn |
7-4 | RESERVED | R | 0h | Reserved |
3-0 | INTCODE | R | 0h | Interrupt code bits. The binary code in INTCODE indicates the event that generated an I2C interrupt. A CPU read will clear this field. If another lower priority interrupt is pending and enabled, the value corresponding to that interrupt will then be loaded. Otherwise, the value will stay cleared. The interrupt events below are listed in descending order of priority. That is INTCODE 1 (Arbitration lost) has the highest priority and INTCODE 7 (Addressed as TARGET) has the lowest priority. In the case of an arbitration lost, a no-acknowledgment condition detected, or a stop condition detected, a CPU read will also clear the associated interrupt flag bit in the I2CSTR register. Emulator reads will not affect the state of this field or of the status bits in the I2CSTR register. Reset type: SYSRSn 0h (R/W) = None 1h (R/W) = Arbitration lost 2h (R/W) = No-acknowledgment condition detected 3h (R/W) = Registers ready to be accessed 4h (R/W) = Receive data ready 5h (R/W) = Transmit data ready 6h (R/W) = Stop condition detected 7h (R/W) = Addressed as TARGET 8h (R/W) = Extended Automatic Clock Stretching |
I2CEMDR is shown in Figure 26-32 and described in Table 26-22.
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I2C Extended Mode
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | NACK_CM | |||||
R/W-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCLKEY | MCS | ECS | FCM | BC | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R/W | 0h | Reserved |
14-9 | RESERVED | R | 0h | Reserved |
8 | NACK_CM | R/W | 0h | NACK Compatibility mode 0: I2CSTR.NACK bit and NACK interrupt gets triggered when NACK is received in Controller Transmitter mode. 1: I2CSTR.NACK bit and NACK interrupt gets triggered when NACK is received in both Controller Transmitter mode and Target Transmitter mode Reset type: SYSRSn |
7-4 | SCLKEY | R/W | 0h | 0xA: Key value which needs to be written to enable Clock (SCL) stretching in ExtendedAuto/Manual mode. Any other value than 0xA: Clock (SCL) stretching mode cannot be enable for both Extended Auto/Manual mode Reset type: SYSRSn |
3 | MCS | R/W | 0h | Manual Clock Stretching mode 0: Manual Clock Stretching is disabled and SCL line is pulled high. 1: Manual Clock Stretching is enabled and SCL line is pulled low allowing software to control clock stretching. Note: When SCLKEY is not 0xA, Manual Clock Stretching mode will remain disabled. Reset type: SYSRSn |
2 | ECS | R/W | 0h | Extended Automatic Clock Stretching mode 0: Extended Automatic Clock stretching feature is disabled 1: Extended Automatic Clock stretching feature is enabled. When enabled, I2C target automatically clock stretches after every ACK / NACK cycle. Note: When SCLKEY is not 0xA, Extended Automatic Clock stretching mode will remain disabled. Reset type: SYSRSn |
1 | FCM | R/W | 0h | Forward Compatibility mode. This bit when programmed brings the functionality of Tx request only when Tx data required regardless of data status in Tx buffer for non-FIFO mode. This register affects the XRDY behavior hence needs to be set after releasing the IRS (I2CMDR[5]). Reset type: SYSRSn |
0 | BC | R/W | 1h | Backwards compatibility mode. This bit affects the timing of the transmit status bits (XRDY and XSMT) in the I2CSTR register when in TARGET transmitter mode. Reset type: SYSRSn 0h (R/W) = See the 'Backwards Compatibility Mode Bit, TARGET Transmitter' Figure for details. 1h (R/W) = See the 'Backwards Compatibility Mode Bit, TARGET Transmitter' Figure for details. |
I2CPSC is shown in Figure 26-33 and described in Table 26-23.
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The I2C prescaler register (I2CPSC) is a 16-bit register (see Figure 14-21) used for dividing down the I2C input clock to obtain the desired module clock for the operation of the I2C module. See the device-specific data manual for the supported range of values for the module clock frequency.
IPSC must be initialized while the I2C module is in reset (IRS = 0 in I2CMDR). The prescaled frequency takes effect only when IRS is changed to 1. Changing the IPSC value while IRS = 1 has no effect.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPSC | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R | 0h | Reserved |
7-0 | IPSC | R/W | 0h | I2C prescaler divide-down value. IPSC determines how much the CPU clock is divided to create the module clock of the I2C module: module clock frequency = I2C input clock frequency/(IPSC + 1) Note: IPSC must be initialized while the I2C module is in reset (IRS = 0 in I2CMDR). Reset type: SYSRSn |
I2CFFTX is shown in Figure 26-34 and described in Table 26-24.
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The I2C transmit FIFO register (I2CFFTX) is a 16-bit register that contains the I2C FIFO mode enable bit as well as the control and status bits for the transmit FIFO mode of operation on the I2C peripheral.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | I2CFFEN | TXFFRST | TXFFST | ||||
R-0h | R/W-0h | R/W-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TXFFINT | TXFFINTCLR | TXFFIENA | TXFFIL | ||||
R-0h | R-0/W1S-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R | 0h | Reserved |
14 | I2CFFEN | R/W | 0h | I2C FIFO mode enable bit. This bit must be enabled for either the transmit or the receive FIFO to operate correctly. Reset type: SYSRSn 0h (R/W) = Disable the I2C FIFO mode. 1h (R/W) = Enable the I2C FIFO mode. |
13 | TXFFRST | R/W | 0h | Transmit FIFO Reset Reset type: SYSRSn 0h (R/W) = Reset the transmit FIFO pointer to 0000 and hold the transmit FIFO in the reset state. 1h (R/W) = Enable the transmit FIFO operation. |
12-8 | TXFFST | R | 0h | Contains the status of the transmit FIFO: xxxxx Transmit FIFO contains xxxxx bytes. 00000 Transmit FIFO is empty. Note: Since these bits are reset to zero, the transmit FIFO interrupt flag will be set when the transmit FIFO operation is enabled and the I2C is taken out of reset. This will generate a transmit FIFO interrupt if enabled. To avoid any detrimental effects from this, write a one to the TXFFINTCLR once the transmit FIFO operation is enabled and the I2C is taken out of reset. Reset type: SYSRSn |
7 | TXFFINT | R | 0h | Transmit FIFO interrupt flag. This bit cleared by a CPU write of a 1 to the TXFFINTCLR bit. If the TXFFIENA bit is set, this bit will generate an interrupt when it is set. Reset type: SYSRSn 0h (R/W) = Transmit FIFO interrupt condition has not occurred. 1h (R/W) = Transmit FIFO interrupt condition has occurred. |
6 | TXFFINTCLR | R-0/W1S | 0h | Transmit FIFO Interrupt Flag Clear Reset type: SYSRSn 0h (R/W) = Writes of zeros have no effect. Reads return a 0. 1h (R/W) = Writing a 1 to this bit clears the TXFFINT flag. |
5 | TXFFIENA | R/W | 0h | Transmit FIFO Interrupt Enable Reset type: SYSRSn 0h (R/W) = Disabled. TXFFINT flag does not generate an interrupt when set. 1h (R/W) = Enabled. TXFFINT flag does generate an interrupt when set. |
4-0 | TXFFIL | R/W | 0h | Transmit FIFO interrupt level. These bits set the status level that will set the transmit interrupt flag. When the TXFFST4-0 bits reach a value equal to or less than these bits, the TXFFINT flag will be set. This will generate an interrupt if the TXFFIENA bit is set. Because the I2C on this device has a 16-level transmit FIFO, these bits cannot be configured for an interrupt of more than 16 FIFO levels. Reset type: SYSRSn |
I2CFFRX is shown in Figure 26-35 and described in Table 26-25.
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The I2C receive FIFO register (I2CFFRX) is a 16-bit register that contains the control and status bits for the receive FIFO mode of operation on the I2C peripheral.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RXFFRST | RXFFST | |||||
R-0h | R/W-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXFFINT | RXFFINTCLR | RXFFIENA | RXFFIL | ||||
R-0h | R-0/W1S-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R | 0h | Reserved |
13 | RXFFRST | R/W | 0h | I2C receive FIFO reset bit Reset type: SYSRSn 0h (R/W) = Reset the receive FIFO pointer to 0000 and hold the receive FIFO in the reset state. 1h (R/W) = Enable the receive FIFO operation. |
12-8 | RXFFST | R | 0h | Contains the status of the receive FIFO: xxxxx Receive FIFO contains xxxxx bytes 00000 Receive FIFO is empty. Reset type: SYSRSn |
7 | RXFFINT | R | 0h | Receive FIFO interrupt flag. This bit cleared by a CPU write of a 1 to the RXFFINTCLR bit. If the RXFFIENA bit is set, this bit will generate an interrupt when it is set Reset type: SYSRSn 0h (R/W) = Receive FIFO interrupt condition has not occurred. 1h (R/W) = Receive FIFO interrupt condition has occurred. |
6 | RXFFINTCLR | R-0/W1S | 0h | Receive FIFO interrupt flag clear bit. Reset type: SYSRSn 0h (R/W) = Writes of zeros have no effect. Reads return a zero. 1h (R/W) = Writing a 1 to this bit clears the RXFFINT flag. |
5 | RXFFIENA | R/W | 0h | Receive FIFO interrupt enable bit. Reset type: SYSRSn 0h (R/W) = Disabled. RXFFINT flag does not generate an interrupt when set. 1h (R/W) = Enabled. RXFFINT flag does generate an interrupt when set. |
4-0 | RXFFIL | R/W | 0h | Receive FIFO interrupt level. These bits set the status level that will set the receive interrupt flag. When the RXFFST4-0 bits reach a value equal to or greater than these bits, the RXFFINT flag is set. This will generate an interrupt if the RXFFIENA bit is set. Note: Since these bits are reset to zero, the receive FIFO interrupt flag will be set if the receive FIFO operation is enabled and the I2C is taken out of reset. This will generate a receive FIFO interrupt if enabled. To avoid this, modify these bits on the same instruction as or prior to setting the RXFFRST bit. Because the I2C on this device has a 16-level receive FIFO, these bits cannot be configured for an interrupt of more than 16 FIFO levels. Reset type: SYSRSn |